LP-HCSL Clock Buffer Output on a Dedicated Clock Input Pin - Arria 10 GX 160

[MSe]

Dear Intel Support Team,

I am having some trouble designing my LP-HCSL Clock Signal to a Dedicated Clock Input,

with regard to the available standards.

My setup:

• Intel FPGA 23.2.0.94 Pro Edition
• FPGA: 10AX016E4F27E3SG
• Primary Clock: Epson SG3225HBN 100 MHz -> HCSL Output
• User Clock (clkusr): Epson SG-8018CE 100 MHz -> 1.8V SE Output
• Clock Buffer: TI CDCDB400 1:4 -> 1 LP-HCSL Input : 4 LP-HCSL Outputs with Rt=85R
• NXP CPU with PCIe 3.0 1 Lane -> LP-HCSL Clock Input Rt=85R

References:

1. AN-891 Driving LVPECL, LVDS, CML and SSTL Logic with “Universal” Low-Power HCSL Outputs

2. Intel ® Arria® 10 Core Fabric and General Purpose I/Os Handbook

My goal is using the clock buffer:

• output 1 to feed the FPGAs system or main clock over a clk_x(p/n) pins
• output 2 and 3 to feed the refclocks of the two ACVR banks
• output 4 to feed the PCIe clock to the CPU

So far I could design 3 of 4 outputs of my clock buffer as intended.

2 of them are routed to the ACVR Banks Ref-Clocks, in QP Pro, the Standard is set to HCSL with OCT=85R.
Also, the PCIe clock to the CPU is fine with Rt=85R.

But when it comes to the FPGA system clock, to one of the clk_ pins, I cannot change the standard to HCSL. So I tried, according to ref. 1, to hook the LP-HCSL signal to the differential SSTL_18 standard, which gave me errors regarding the pseudo differential signal standard.

So I changed the standard to LVDS, according to ref. 2 (5.5.5.2. Differential I/O Termination for Intel Arria 10 Devices).

But it seems, If I set up the OCT to 85R, during compilation the OCT is set off.

So now I am a bit confused, on how to design my LP-HCSL output to a LVDS clk_ input.

My actually questions:

1. Do I need external AC-Coupling?
2. Do I need external biasing?
3. Do I need external termination? like an external Rt=85R in front of the clk_ input
4. Can I even change the OCT to 85R? Or just 100R and off?
5. Can I design the LP-HCSL output to the LVDS clk_ input as shown in ref. 1 figure 12?
   (but with 85R / 42.5R instead of the shown 100/50R)

Could you please give me advice? Or point me to an example?

In the eval boards I could find, they're only using LVDS to LVDS with the clock domains.

Thanks in advance

Marcel

[FvM]

Hi,

my suggestion is, make it simple. A10 LVDS input can receive HCSL clock at 100 MHz directly due to wide common mode range. There's no 85 ohm differential termination, but it's  not necessarily required.

[MSe]

Thanks @FvM for your feedback.

You are reading my mind, keeping it simple is exactly where I wanna go.

So setting an OCT=85R with or without calibration is not possible,

also the Receiver Rx OCT is just for the ACVR Banks, not for the I/O Banks.

Leaves me to just one choice, switching the LVDS Input Termination to OFF,

and placing a 85R or rather 84.5R close to the clk_ pins.

I hope by switching the termination to Off, it doesn't mess with the DC biasing.

Regards

Marcel

[AqidAyman_Intel]

Hi Marcel,

Any update on the suggestion from @FvM? Have you tried it?

[MSe]

Hi @AqidAyman_Intel ,

thanks for keeping up with me on this topic.

The Arria 10 docs seems to me a little bit inconsistent or rather incomplete regarding the

DC-Bias and termination for the none ACVR Banks. So I assumed the worst and designed

a DC-Bias in my schematic. With the first PCB batch I will see if it's working as intended.

Best

Marcel

[AqidAyman_Intel]

Hi Marcel,

Thank you for the confirmation.

Regards,

Aqid