Hi,
I work as a hardware designer. In my design, I used an Arria10 FPGA and an LRDIMM DDR4 module. I connected an FPGA to a processor using PCIe x8.
The procedure is as follows: the FPGA receives certain Display port data from various devices, and the FPGA must write to the DDR4 LRDIMM Module (256Gb). This Processor will read the signal through PCIe x8 after the write. The processor will then write data to DDR4 through DMA in the FPGA.
The problem is that the processor can read DDR4 data from the FPGA but not write it. Is there anything I need to change in the Quartus prime tool? What all settings must be checked.
I have several boards, and only one of them is operational. The second is that it works sometimes and does not function other times. The remaining sets are completely ruined. From the hardware perspective there are no problems in the power or any issue.
Pl suggest.
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Hi!
I'm Adzim from Intel Support will assist you in EMIF area.
First of all, please check the memory module and device are working properly.
You can generate an EMIF Example Design to test the memory device.
Please take a look at the timing report after the design is compiled. If there are some timing violations occurred, then the design need verify for fixing the timing issue first.
There is an PCIE example design for Arria 10 device that I think you can use for debugging purpose.
So you can check if the write and read can be performed through the DMA.
You may visit Intel FPGA Design Store to get the Design Example.
Regards,
Adzim
Hi !
Actually, we have done DDR4 calibration on every board and that is working perfectly but with all the functionality integrated JIC has the issue,
We are able to read the data from DDR4 through PCIe and we compared the same from the FPGA and Jetson DVK. Its matching, So read activity is performing but the write has the issue.
Hi!
Thank you for your update.
Can you share some snapshots of the failing issue?
Are you performing write DMA manually or automatically?
Are you able to verify that the data is ready when performing write?
Regards,
Adzim
Hi,
Our FPGA team did an exercise, Reading and writing to DDR4 from FPGA for 8GB without DMA access, this part is working. So I suggested doing 64GB and 128GB data read and write. The 64GB and 128GB is read and write is working as expected.
Could you pl let me know what all screen shot required?
Hi,
Thanks for the update.
Just want to clarify here, the current issue that you're facing is the write DMA is not performing well?
Can get any snapshot or error log that you get when performing the write DMA?
Thank you.
Hi AdzimZM,
We have tested DDR4 128GB write and read from the FPGA directly and it is working. Yet to test the same through the DMA, We are enabling the DMA from the firmware and Writing 128GB from the FPGA and Reading it through Read DMA Then cross verify. Once after this testing then I will post the reply.
Hi @malayali ,
Thanks for the feedback.
If there any issue found during the test, please capture some snapshot of the issue encounter.
Thanks!
Regards,
Adzim
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