LVDS (2.5V) in Banks where JTAG and Config Pins reside?

[Altera_Forum]

Hello, 

 I want to use the Bank 2, 5 and 6 of the Cyclone II EP2C35F484 for LVDS communication. An FAE from Sasco Holz (Arrow) told me, that i should use the left and right banks for LVDS instead of the top and bottom banks, maybe because of the "Low Jitter" (L) output Pins of the PLL that is need for LVDS. The problem is, that the Dedicated Programming and JTAG Pins also reside in bank 2 and 6. For LVDS i need a VCCIO Voltage of 2,5V. What about the Voltage for the Programming an JTAG Pins in these banks? Do they work with 2,5 Volt or is it absolutely necessary to use a VCCIO of 3,3 Volt at banks, where Programming and JTAG Pins reside?   Thanks in advance!     Stefan   PS: I use Quartus 8.0 SP1   

[Altera_Forum]

You can use VCCIO of 2.5V for JTAG and configuaration. All pull-up resistors and JTAG connector VCC should be wired to the respective VCCIO voltages. There may be a problem with Altera AS devices, that are not available with other supply voltages than 3.3V up to now. Output pins to AS memory should reside in a 3.3V powered bank by specification, otherwise the high level margin would be too low.

[Altera_Forum]

I have similar problem, I need 3.3V for JTAG for other device. Is there any way to set LVDS voltage to 3.3V? I work with Cyclone III. 

Thanks

[Altera_Forum]

Hi Szymo, 

 as far as I know, you can supply the LVDS Banks VCCIO with 3,3V while choosing LVDS as I/O Standard. If you do so, you are not longer LVDS compliant, but if the Partner Device is also a Cyclone FPGA it should work properly. I used a Cyclone II as a Parallel to LVDS Interface for an LVDS Display. The Display´s National Semiconductor LVDS Chip works inside its specification even if you power the LVDS Bank with 3,3 Volt.  If you are not sure, why don´t you put the LVDS Pins into a Bank where no JTAG Pins resides in?  Sometimes it´s helpful to have a look at the Pin Connection Guidelines from Altera. For Cyclone III you can find it here: http://www.altera.com/literature/dp/cyclone3/pcg-01003.pdf  I hope i could help you.  Stefan

[Altera_Forum]

The problem is, that LVDS driver as well as receiver behaviour for 3.3V VCCIO is completely unspecfied. If it works in your design, possibly with an non-LVDS compliant VCM level, you can't be sure, if it's only working by chance. I would expect, that it's O.K. for reduced speed requirements, but it's more or less guessing. 

 It's much easier to operate the JTAG interface with VCCIO of 2.5V, all JTAG inputs can be interfaced with a 3.3V JTAG chain, only TDO may need a buffer for level translating, but only, if the next device in the chain can't work with 2.5V input level as well.

[Altera_Forum]

--- Quote Start ---  all JTAG inputs can be interfaced with a 3.3V JTAG chain  --- Quote End ---  But when banks have VCCIO = 2.5V and JTAG input signals have VCC = 3.3V don't I need Schottky diodes?

[Altera_Forum]

Take bank 6 for example.Some configuration pins(MSEL,CONF_DONE) should be pull up tu VCCA.VCCA here stands for VCCIO in the bank these pins reside in.So,if we use IO from bank 6 as LVDS,we just wire VCCIO_bank6 ,MSEL and CONF_DONE to 2.5v.Level translating isn't needed for bank 6.Am i right?