I need to interface with an image sensor which outputs dual LVDS buses, each bus is 8 data lanes + 1 sync + 1 clock. Each lane operates up to 800 Mb/Sec in DDR mode, i.e. the clock is up to 400 MHz.
I'm looking for low cost FPGA that can connect to such sensor, i.e. have the option for LVDS RX with DDR capability.