Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
21602 Discussions

LVDS Register outputs...

Altera_Forum
Honored Contributor II
‎06-13-2014 09:35 AM
1,283 Views

Hi FOlks, 

 

THis is probably an easy one for someone to explain: 

 

In the altlvds_rx moduloe, what does the 'register outputs' actually do/mean??? 

 

many thanks 

D
0 Kudos

Link Copied

1 Reply
Altera_Forum
Honored Contributor II
‎06-13-2014 09:46 AM
485 Views

Hi deBoogle,  

 

This is an option to put a barrel register to synchronise parallel data output or not directly inside the IP. If not it's recommended to put one outside the IP. 

 

Regards, 

Romain
0 Kudos
Copy link
Reply

Community support is provided Monday to Friday. Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.