LVDS SERDES Routing problems

[CHatz]

I am using Quartus Standard 18.1 to process a design for the Arria 10.  Two SERDES IPs are used to receive serial data from high speed A/D Converters. The signals from each ADC are routed to two I/O banks.

4 data inputs from each ADC converter cannot be placed in the specified pins. A sample of the errors being generated is shown below:

Error (175020): The Fitter cannot place logic LVDS_CHANNEL that is part of epl_pcl_egl_a10_rev2_0 BSM_EPL_PCL_EGL_A10_wrapper in region (84, 7) to (84, 17), to which it is constrained, because there are no valid locations in the region for logic of this type.
Info (14596): Information about the failing component(s):
Info (175028): The LVDS_CHANNEL name(s): soc_system_a10_rev2_new:soc_inst|BSM_EPL_PCL_EGL_A10_wrapper:epl_pcl_egl_a10_rev2_0_0|BSM_EPL_PCL_EGL:b2v_inst|ad9212_sperry_2adc:b2v_inst_A10_ADC1_2|lvdsrx10x9:deser|lvdsrx10x9_altera_lvds_181_rkjbrlq:lvds_0|lvdsrx10x9_altera_lvds_core20_181_yvd5cci:core|altera_lvds_core20:arch_inst|channels[2].dpa_fifo.serdes_dpa_inst~CHANNEL
Error (16234): No legal location could be found out of 1 considered location(s). Reasons why each location could not be used are summarized below:
Info (175015): The I/O pad adc2_ch10_d is constrained to the location PIN_AE16 due to: User Location Constraints (PIN_AE16)
Info (14709): The constrained I/O pad is contained within a pin, which is contained within this LVDS_CHANNEL
Error (175006): Could not find path between source IOPLL and the LVDS_CHANNEL
Info (175026): Source: IOPLL soc_system_a10_rev2_new:soc_inst|BSM_EPL_PCL_EGL_A10_wrapper:epl_pcl_egl_a10_rev2_0_0|BSM_EPL_PCL_EGL:b2v_inst|ad9212_sperry_2adc:b2v_inst_A10_ADC1_2|lvdsrx10x9:deser|lvdsrx10x9_altera_lvds_181_rkjbrlq:lvds_0|lvdsrx10x9_altera_lvds_core20_181_yvd5cci:core|altera_lvds_core20:arch_inst|altera_lvds_core20_pll:internal_pll.pll_inst|altera_lvds_core20_iopll
Info (175021): The IOPLL was placed in location IOPLL_3B
Error (175022): The LVDS_CHANNEL could not be placed in any location to satisfy its connectivity requirements
Info (175029): 1 location affected
Info (175029): LVDS_CHANNEL containing AE16

I am attaching a file with all the errors generated by the Fitter and a screen shot of the PIN Planner with the LVDS SERDES signal inputs.

[CHatz]

Since I am using the SERDES receivers in DPA mode and the refclkin should be connected to an IOPLL, I have changed the constraint for the high speed clock to an input (as described in the documentation) that connects to an IOPLL. 

However, this time the Fitter generates an error for an invalid placement. See errors below:

Error (14566): The Fitter cannot place 2 periphery component(s) due to conflicts with existing constraints (2 pin(s)). Fix the errors described in the submessages, and then rerun the Fitter. The Intel FPGA Knowledge Database may also contain articles with information on how to resolve this periphery placement failure. Review the errors and then visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.
Error (175020): The Fitter cannot place logic pin in region (150, 36) to (150, 44), to which it is constrained, because there are no valid locations in the region for logic of this type.
Info (14596): Information about the failing component(s):
Info (175028): The pin name(s): adc1_dco
Error (16234): No legal location could be found out of 1 considered location(s). Reasons why each location could not be used are summarized below:
Error (18805): No dedicated path available for refclk signal, adc1_dco. Please promote your refclk to a global clock or move it to a dedicated IOPLL refclk pin. (1 location affected)
Info (175029): pin containing PIN_R2
Info (175015): The I/O pad adc1_dco is constrained to the location PIN_R2 due to: User Location Constraints (PIN_R2)
Info (14709): The constrained I/O pad is contained within this pin
Error (175020): The Fitter cannot place logic pin in region (84, 9) to (84, 17), to which it is constrained, because there are no valid locations in the region for logic of this type.
Info (14596): Information about the failing component(s):
Info (175028): The pin name(s): adc2_dco
Error (16234): No legal location could be found out of 1 considered location(s). Reasons why each location could not be used are summarized below:
Error (18805): No dedicated path available for refclk signal, adc2_dco. Please promote your refclk to a global clock or move it to a dedicated IOPLL refclk pin. (1 location affected)
Info (175029): pin containing PIN_AC16
Info (175015): The I/O pad adc2_dco is constrained to the location PIN_AC16 due to: User Location Constraints (PIN_AC16)
Info (14709): The constrained I/O pad is contained within this pin
Error (15307): Cannot apply project assignments to the design due to illegal or conflicting assignments. Refer to the other messages for corrective action.
Error (16297): An error has occurred while trying to initialize the plan stage.
Error: Quartus Prime Fitter was unsuccessful. 10 errors, 73 warnings
Error: Peak virtual memory: 6608 megabytes
Error: Processing ended: Mon Feb 03 17:21:59 2025
Error: Elapsed time: 00:01:13
Error: Total CPU time (on all processors): 00:01:09

I am attaching the A10_Handbook Figure for SERDES with DPA enabled, which I use for the LVDS SERDES IP, and screen capture of the PIN PLANNER with the SEDRDES IP pin inputs.

[FvM · Accepted solution]

Hi,
there are basically two requirements
- SERDES must use an IOPLL in the same bank
- IOPLL must be driven by a dedicated REFCLK pin in the same bank

adc1_dco is apparently no REFCLK pin, adc2_dco isn't shown in the screenshot.