LVDS SERDES doesn't work

[Altera_Forum]

I'm using Arria-10 to make a LVDS SERDES. But it doesn't work. Looking forward to your help. 

The code is as below. Please see the attached pdf for how SERDES IP is configured.   signal FL_Clk : std_logic; signal FL_Channel0 : std_logic_vector(6 downto 0) := (others => '0'); signal FL_Channel1 : std_logic_vector(6 downto 0) := (others => '0'); signal FL_Channel2 : std_logic_vector(6 downto 0) := (others => '0'); signal FL_Channel3 : std_logic_vector(6 downto 0) := (others => '0'); signal LVDSOut : std_logic_vector(4 downto 0) := (others => '0'); -- LVDSOut(3 downto 0) = Channel 0..3 LVDSOut(4) = Clock i0_Serdes : SERDES port map ( tx_in => FL_Channel3 & FL_Channel2 & FL_Channel1 & FL_Channel0, -- tx_in.export tx_out => LVDSOut(3 downto 0), -- tx_out.export tx_outclock => LVDSOut(4), -- tx_outclock.export inclock => Clk_125mhz, -- inclock.export --pll_areset => Reset, -- pll_areset.export pll_areset => Reset_flu, pll_locked => open, -- pll_locked.export tx_coreclock => FL_Clk -- tx_coreclock.export ); -- Output g_out: for i in 0 to 4 generate i_out: diff_out port map( din => LVDSOut(i downto i), pad_out => localdisplay_dp(i downto i), pad_out_b => localdisplay_dn(i downto i) ); end generate;

[Altera_Forum]

A further quesiton: Do all LVDS pins on Arria-10 support the serdes option?

[Altera_Forum]

Hi softwind555, 

 Mind share further on what is the failure observation? Just wonder if you observe the failure in simulation or hardware?

[Altera_Forum]

--- Quote Start ---  Hi softwind555,  Mind share further on what is the failure observation? Just wonder if you observe the failure in simulation or hardware?  --- Quote End ---    I'm using the scope to capture the clock output on "localdisplay_dp(4)" pin. But, i get nothing on it. I'm expecting a 33MHZ clock on this pin.

[Altera_Forum]

Hi softwind555, 

 I believe it would be great to try your design with Modelsim simulation to isolate out any functional issue. You can pay specific attention to the SERDES signals ie reset, pll_locked, tx_outclock to see if there is any anomaly.

[Altera_Forum]

Hi softwind555, 

 Did you check if there are any inclk 125MHz? Also did your reset pull high or pull low?  Not all the GPIO support the LVDS serdes though, you might need to look into pin with DIFFIO function in them. You can find that in the pin planner or the pinout file. Also I do not think you will need the g_out. You can straight away assign the lvdsout as an output pin. Then make sure all your pins are connected on the board.

[Altera_Forum]

The transmitter model doesn't work at all. 

I tryed thee most simple model with internal PLL. I can see that the internal PLL is locked but nothig comes out.  The receiver works fine.    César

[Altera_Forum]

--- Quote Start ---  The transmitter model doesn't work at all.  I tryed thee most simple model with internal PLL. I can see that the internal PLL is locked but nothig comes out.  The receiver works fine.    César  --- Quote End ---    Is this observed at both simulation and hardware?

[Altera_Forum]

By the way, you might also want to double check on the pinout just to isolate this out.

[Altera_Forum]

In simulation. I'll try soon the hardware.

[Altera_Forum]

--- Quote Start ---  In simulation. I'll try soon the hardware.  --- Quote End ---    Do you observe any abnormal messages when compiling the libraries in simulation? It seems weird to have no output from the LVDS in simulation. You might also want to try filing service request.

[Altera_Forum]

ModeSim gives me no errors or warnings. 

Try yourself to simulate a very simple model using internal PLL. I used Quartus II and ModelSim.

[Altera_Forum]

--- Quote Start ---  The transmitter model doesn't work at all.  I tryed thee most simple model with internal PLL. I can see that the internal PLL is locked but nothig comes out.  The receiver works fine.    César  --- Quote End ---    I´m having some problem with the transmitter too, I'm not using the receiver. I'm getting nothing as result in my data output from the TX when I look at the signalTap, I already tried with external PLL option and without it, did u find any solutions for the  transmitter?  I configured the output pins using the HSMC, but got no response.