I can instantiate more IOPLLs in my Arria 10 design (device 10AS016E4F29I3SG) than should be available. According to the documentation (https://documentation.altera.com/#/00035112-nt$nt00068592), the SX 160 has 6 IOPLLs. However, I was able to synthesize and fit a design with 8 IOPLLs. I have checked the fitter report: all 8 IOPLLs have different locations.Are there really more than 6 IOPLLs in the target device? Or how can this discrepancy between documentation and fitter be explained?
You have 12 PLLs in that device - 6 fractional and 6 integer. Perhaps it's used a fractional PLL...However, I appreciate you're stating it's reporting "8 IOPLLs" - which doesn't particularly stack up. In which case, perhaps there is a discrepancy between the docs and the fitter - it does occasionally happen. Only Altera will be able to comment on that. Cheers, Alex
Thanks for your reply, Alex. I think the fitter merged several logical PLLs into one physical PLL. The fitter report was misleading as it reported the instantiation of IOPLLs in I/O banks that do not exist in the device used. When using pins as refclk input, the fitter was not able to fit 8 IOPLLs into the device anymore.