Hello,
I have an application with Stratix III with 4 FPGAs with LVDS inter-connects. One (master) processor provides data for the other 3 (slave) processors and they send data back concurrently. Everything is synchronised (at least there is no need for it not to be so).
In the master, I have created 3 transmit LVDS blocks using serdes fed from the same external clock pin (so they share a PLL). I intend to have 5 LVDS data bits plus 1 LVDS clock signal wired to each of the 3 slave FPGAs (with matched trace lengths/characteristics).
In each of the 3 slave processors, I intend to connect the received clock from the master to an Rx serdes (to recover the data from the master) and to a Tx serdes to send data back to the master.
My question is: what do I need to wire up in the return direction from each slave back to the master?
Can I just connect 5 LVDS data bits without a clock? i.e. assume that because the return data is synchronised with the master that the Rx serdes on the master can be driven by the same clock as the Tx serdes on the master
or
should I send a clock back from each of the 3 slaves (but this would imply using a PLL for each clock to recover the data and this will surely NOT fit).
I unserstand that I may need to enable DPA or at least manually tweak the phase alignment in the master and slaves to account for propogation delay and skew.
I'm working at 500Mbits/sec on each data line (or at least that is my intention).
Will this system work?? (I'm doing the circuit and firmware so I can't test this yet - we don't have any SIIIs yet anyway!)
Any advice???
