LVDS clock outputs

[Altera_Forum]

Hi all,  

 We use Stratix-IV GX (EP4SG360FF35C4) device.   1. How to specify the PLL output clock as LVDS in altpll? (This device doesn't supports "Setup PLL in LVDS mode" option).   2. Our design needs 6 LVDS clock output signals. All the clocks should be from PLL only (for sync with the LVDS data) and as per the board requirement, design should be at the right side of the FPGA.   We have only 6 PLL in the device and can't use all the PLLs, because some other modules also need PLLs. How can we take the 6 LVDS clock outputs from PLL?

[Altera_Forum]

Just use regular I/O. You don't need those dedicated PLL outputs, and if it's source synchronous outputs, then you definitely don't want them as they don't match the data. (I see very high speed interfaces using regular I/O to send out clocks all the time.) Are you using altlvds?

[Altera_Forum]

Hi, Thanks for your reply. 

 Since the interface is DDR, I need to maintain the data-clock relationship. So, I need to constrain the each data with respect to their clock outputs. I don't use altlvds.     Just use regular I/O. You don't need those dedicated PLL outputs, and if it's source synchronous outputs, then you definitely don't want them as they don't match the data. (I see very high speed interfaces using regular I/O to send out clocks all the time.) Are you using altlvds?

[Altera_Forum]

I suggest that rather than drive the clocks out directly from the PLL or through other I/Os, you use a 1-bit ALTDDIO_OUT MegaWizard for each of the clock outputs. When you do this, tie the HI data input to '1' and the LO data input to '0', and the same clock that is driving the data out to the select input. This will give you and edge-aligned clock. If you want center-aligned clock outputs, then shift the clock to the ALTDDIO_OUT by 90 degrees from the clock driving the data out. Using the ALTDDIO_OUT registers to drive your clock out will give you the lowest possible skew between your clock and your DDR data outputs.

[Altera_Forum]

Hi all, 

I tried to implement this in a Cyclone II device, the way Jimbo recomended. For some reason the altDDIOs registers are not place in the IO cell, but logic cell out side it (see in the Chip Planner)  I have attached a simple example of what I'm fighting with  Cheers Stefan

[Altera_Forum]

--- Quote Start ---  For some reason the altDDIOs registers are not place in the IO cell, but logic cell out side it (see in the Chip Planner)  --- Quote End ---   The Cyclone II device manual clarifies:   --- Quote Start ---  The DDR output logic is implemented using LEs in the LAB adjacent to the output pin.   --- Quote End ---  

[Altera_Forum]

Humm okey. Would it still be better for slew rate to use the AltDDIO implemented in logic cell than feeding the pll clock directly to the LVDS IO?