LVDS cycloneII to 10 bit counter

[Altera_Forum]

In cycloneII manual i read the max freq input LVDS pin is >800MHz. 

 IF i have a 750 MHZ signal as input, and i send it to LVDS input (cycloneII), can i divide this freq with a 10-bits counter?   Regards, Thieulam

[Altera_Forum]

Hi Thieulam, 

   --- Quote Start ---   In cycloneII manual i read the max freq input LVDS pin is >800MHz.   IF i have a 750 MHZ signal as input, and i send it to LVDS input (cycloneII), can i divide this freq with a 10-bits counter?    --- Quote End ---  Division is the term usually applied to reducing the frequency of an external clock. I think that what you are really asking is about serial-to-parallel conversion of a data stream. The LVDS SERDES receiver blocks (ALTLVDS) can perform serial-to-parallel conversion, and I believe 1:10 is a supported mode. In general, the ALTLVDS component needs a data lane (or lanes) and a reference clock. In your case, you would have a 75MHz reference clock, a 750Mbps data lane, and 1:10 serial-to-parallel conversion mode.   You should use Quartus to configure an ALTLVDS component for your target device. Quartus will check that your data rates are compatible with the FPGA speed grade you have selected for your project.  If the Cyclone II part does not work, the Stratix II can support over 1Gbps data rates, as do newer Stratix series devices. The newer Cyclone series devices are probably faster too.  Cheers, Dave

[Altera_Forum]

Hi Thieulam, 

 If it really is a 750MHz clock signal that you want to slow down, then it is too fast for the FPGA I/O pins. You would need an external divider. Micrel make plenty of high-speed dividers.  Check the Cyclone II data sheet for the PLL specifications. You could divide your clock down to the PLL reference fmax, and then route the divided signal to a PLL reference pin. Alternatively, divide the clock down to below the I/O pin maximum frequency.  What do you hope to do with this signal once you get it into the FPGA?  Cheers, Dave

[Altera_Forum]

tnx to all. 

 i Need to measure microwave frequency of a pulsed signal. The freq range is 5.4GHz-5.9Ghz, and the width pulse is 0.5uSEC(min). I have got an external prescaler divider (div8).   example for f=5.6GHz: width=0.5uSEC   5.6Ghz/8= 700MHz   in a time of 0.5uSEC i have 350 pulses.   if i measure with a counter (9 bit counter in this case) these pulses number, i can measure the frequency.

[Altera_Forum]

Hi Thieulam, 

 So the design requirement is really, measure the frequency or number of transitions on a signal in 0.5us. The signal frequency is 5.4GHz/8 = 675MHz to 5.9Ghz/8 = 738MHz.  This signal is essentially asynchronous relative to the FPGA clock domain.  Given that the signal is pulsed, you cannot use it to lock a PLL.  The pulse frequency is too high for the clock reference pins on an FPGA. Can you divide it one more time? Eg., use an external divide-by-16?  If you can reduce the frequency to the point where you can get the signal onto an FPGA clock pin (or I/O pin if the fmax of the pin is not violated), then internally you can create the following logic;  You need an accurate FPGA clock; this will be used to generate a reference gate signal. The gate signal needs to assert when the pulse starts, and stay asserted for the length of the pulse. For example, lets say an incoming pulse 'triggers' your gate signal, which is then enabled for 0.4us, during which time the incoming pulse clocks a counter. The count at the end of the pulse then determines the incoming frequency.  The tricky part is generating the gate pulse. I'd try something like the following; use a register that gets 'set' by an incoming pulse clock edge, i.e., this would get set when the first pulse clock edge arrives. Synchronize that to the FPGA clock domain, and use that to enable the generation of a 0.4us enable pulse from the accurate FPGA clock domain. Then use the pulse clock edges to synchronize the 0.4us pulse in the pulse clock domain. Use the synchronized signal to enable the pulse clock edge counter. At the end of the 0.4us count, generate a handshake back to the FPGA clock domain indicating that the counter count is valid and stable. Read the count in the FPGA clock domain, and you can then determine the pulse frequency. Clear the register that was 'set' by the initial pulse edge (this will need to be an asynchronous reset, since there is no clock in the other domain when there is no pulse).   Cheers, Dave

[Altera_Forum]

excellent idea! 

 do you think that we can use more repetitions of pulses to improve the measure??

[Altera_Forum]

--- Quote Start ---   do you think that we can use more repetitions of pulses to improve the measure??   --- Quote End ---  If each measurement is a random variable, then averaging can improve your estimate of the mean. However, its up to you to determine what the statistics of the measurement are. I would recommend first implementing a design where you can capture the timing of every single pulse. Transfer that data to a PC where you can analyze it in say MATLAB. Plot a histogram of the data for a fixed pulse setting. However, even this setup may not be realistic, since you have not described in detail what is generating the pulses for you to measure.  Create a simulated signal source that is representative of the signals you wish to measure. Then perform averaging to see if you obtain a more accurate measurement.   Since you have not described how accurate your measurement must be, and over what timescale, there's little we can comment on.  Cheers, Dave