'Leaving target processor paused'

[Altera_Forum]

When I used the nios-ide (in Ubuntu 10.10), I met a error message below. 

 /opt/altera/10.1sp1/nios2eds/bin/nios2-download: 24: function: not found cd: 55: Illegal option -- eval: 1: search_for_jdi: not found Using cable "USB-Blaster [USB 2-1.1]", device 1, instance 0x00 Pausing target processor: OK Initializing CPU cache (if present) OK  Downloading 00008000 ( 0%) Downloaded 2KB in 0.0s   Verifying 00008000 ( 0%) Verified OK  Leaving target processor paused   Can anyone tell me to how to deal with this problem?

[Altera_Forum]

Ubuntu and debian have linked /bin/sh to a reduced version of bash (dash), and the altera tools expect to have a bash complete implementation in /bin/sh 

 Maybe changing this will make the tools behave well again

[Altera_Forum]

--- Quote Start ---  Ubuntu and debian have linked /bin/sh to a reduced version of bash (dash), and the altera tools expect to have a bash complete implementation in /bin/sh  Maybe changing this will make the tools behave well again  --- Quote End ---    Thanks for your helpful reply! I used a command like 'sudo ln -sf /bin/bash /bin/sh' to change to use the bash. And I tried again. Some errors were solved. But there were some errors yet!  The error messages were below  Using cable "USB-Blaster [USB 2-1.1]", device 1, instance 0x00 Pausing target processor: OK Initializing CPU cache (if present) OK Downloading 00008000 ( 0%) Downloaded 15KB in 0.1s  Verifying 00008000 ( 0%) Verify failed between address 0x8000 and 0xBBB3 Leaving target processor paused  This was a very sample program. I used the template 'hello world' in the nios2-ide. In the sopc builder, I used the on-chip memory, and auto-assign base address. The address 0x8000 and 0xBBB3 is on-chip memory.  But why verify failed?

[Altera_Forum]

When i found this problems with my own designs would be, all the time, that i have surpased the fmax acceptable for the system/FPGA i was running on 

 Maybe with a time constraining you will fix this.  What i have found to work is (obviously) to low the clock speed to slower values.  (For example, NIOS II running over 110 MHz in a 7 speed grade Cyclone II would fail to verify; after making the clock 100MHz, it would run find)

[Altera_Forum]

--- Quote Start ---  When i found this problems with my own designs would be, all the time, that i have surpased the fmax acceptable for the system/FPGA i was running on  Maybe with a time constraining you will fix this.  What i have found to work is (obviously) to low the clock speed to slower values.  (For example, NIOS II running over 110 MHz in a 7 speed grade Cyclone II would fail to verify; after making the clock 100MHz, it would run find)  --- Quote End ---    Thanks for your reply! Your message is very helpful. But I think my problem is about the nios2eds for Linux version. Because I downloaded the nios2 sys using Windows version, and it ran well.But I downloaded the same project using the Linux version, it couldn't run well. Maybe there were some error when I installed the Linux version, and some .so file couldn't be found. And I use the command 'sudo ln -sf ' to link the .so file.But I thought there were some other errors.  Maybe the nois2eds for Linux version does not work well on Ubuntu, and maybe it will work well on the RedHat. I had change to the Windows xp. After accomplishing my project which my teacher assigned to me, I will try to solve it.  And thanks to you again.You message is really helpful. If you installed the nios2eds on Ubuntu, please share your installation experience to me!