CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
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I found LVDS receiver in Stratix II DO NOT need a bit clock, just frame clock is OK. and LVDS receiver in Stratix II will regenerate the bit clock needed by using frame clock.
altlvds_rx Megafunction by default includes instantiation of a PLL that generates bit clock from frame clock. With source synchronous transmission, only a frame clock is available normally. Regards, Frank
