LVPECL VCCIO 3.3V instead of 2.5V

[Altera_Forum]

Hi, I am facing an issue for my PCB which uses Arria2GX FPGA. Due to pin constraints, I am forced to use an LVPECL dedicated clock on a bank which has LVCMOS33 I/Os(Bank 4A for EP2AGX125E device to be exact). I have provided VCCIO as 3.3V but LVPECL (which shares the same VCCIO) requires VCCIO not greater than 2.6V. will this be an issue and cause the clock receiver to fail? I cannot use any other banks because all other clock input pins are used.

[Altera_Forum]

Apart from the question, if the differential receiver possibly can work with VCCIO of 3.3V and which performance degradation must be expected, Quartus will require a VCCIO setting of 2.5V for the respective bank to allow an differential I/O standard in it. So you would have to declare all LVCMOS I/Os of bank 4A wrongly as LVCMOS25 in addition. 

 But you can hardly expect official clearance for unspecified operation of Altera devices, I think.

[Altera_Forum]

FvM, thanks for your reply.  

 Yes, the person who compiles the FPGA build has decided to falsely give LVCMOS25 and generate the build. For LVCMOS this won't be an issue I guess, since noise margins are almost compatible for LVCMOS33 and LVCMOS25. But my worry is whether the 3.3V would cause the LVPECL receiver to malfunction. I am using AC coupling and the differential swing is within the range of Altera spec. Besides, the common mode bias which I have provided is 1.25V(assuming 2.5V).. since the supply is now 3.3V, should I increase the bias? I still think 1.25V is pretty safe even with 3.3V.

[Altera_Forum]

Personally, I expect the receiver to work at 3.3V, the maximum speed most likely reduced. Because Altera won't give a specification for differential receiver operation at 3.3V, you have to acquire the typical data yourself, provide a sufficient margin and hope, that it isn't ruined by device parameter variations.