Hi,I made custom QSYS component in QSYS Quartus II 16.1. To validate it I open project in QUARTUS II 17.1 Lite Edition. During compilation process I received the message: ...x_ctrl/synthesis/submudules/x_ctrl_cpu_cpu.v is OpenCore Plus time-limited file. Remove the unlicenses cores or obtain license for those OpenCore Plus time-limited IP cores. All design is my one. How can I avoid these problems? Best Regards,Tgel.
Just as it says, you need a license for the IP. Is that a Nios II processor? You should be able to compile and run the design on the board in OpenCore Plus mode (keep the JTAG connection active). What is the IP that the error is referring to?
Hi,My QSYS component uses single IP which is counter IP and I haven't any problem with it. My design hasn't any others IP. I made it robust for any kind of FPGA from any companies. Why do I obtain problem with licences for my own design in Quartus 17.1 lite edition? Best Regards,Tgel111
Is the file from the error message one of your own, or an Altera IP? Check that you still don't have some other IPs in your project that require a license, in the Project files list. Check also that you have included the correct Qsys system in your project, and generate the qsys module once more, in case it is still an old version that Quartus is trying to compile.
hI,I generated qsys component from beginning and obtained the same license error:...x_ctrl/synthesis/submudules/x_ctrl_cpu_cpu.v is OpenCore Plus time-limited file. Remove the unlicenses cores or obtain license for those OpenCore Plus time-limited IP cores. The file from the error message is altera's file. I used in QSYS file except my own component: clock,niosII,jtag_uart,ram,PIO-led,PIO-pb,sysid. In my component I used counter IP only. I didn't use any others IP include OpenCore IPs. Best Regards,Tgel111