Link to SRAM Qsys Tutorial 8 Bit sought

[Altera_Forum]

Hmm 

 like many others I'm stunned at how difficult it is to add an SRAM component to a NIOS system. Two days and  so far all I can get is a mishmash of signals that seem to bear no relation to the pins I specified.   Does anyone have a link to the absolute simplest - latest version Qsys - No problems with 'unasserted clock' stuff - 512k x 8 SRAM. The absolute simplest - including how to attach the pin numbers properly - I must have been through pin planner a dozen times and sometimes it insists on deleting everything I've done.  I've had it as far as writing signals to some of the SRAM pins but they seem to bear no relation to the pin numbers I connect to in the BDF.  I don't doubt I'm very new to Altera and Qsys but getting this SRAM business working really seems to be a step beyond - I was expecting a couple of hours work :(   Sorry for the downhearted tone - was getting on so well with it all but like a lot of others the complexity involved for this '1st step' of adding RAM is very steep.   Thanks to anyone that can help out - it really is hair tearing stuff isn't it.  Pete   I've been working through with this guide:  http://www.cs.columbia.edu/~sedwards/classes/2013/4840/lab3.pdf  I'll also have a look at this recent post which seems to show an 8 bit system.  http://www.alteraforum.com/forum/showthread.php?t=40732&highlight=sram+8+bit   The main issue I'm having is how to define the pin assignments and lock them down - preferably programatically rather  than use the GUI - I'm finding that some way that I'm working with Quartus is resulting in the assignments being remade  every so often - if the pins are unused at that point on the BDF the assignments lose all directional settings for example.  If I do use the GUI - which of the screens do I lock the Pin assignments down in - the Assignment Editor or Pin Planner?   I've seen the importing assignments file option but is there any file that I can just open and save in an editor tht will get picked  up by the compilation train?

[Altera_Forum]

An Update - please if anyone has any extra information - I am really trying hard here but no joy. 

 I have tried three different methods each with the same (or similar) result - Address lines working away fine when running a small test C program writing to the correct memory locations.  But no data writes occurring. No activity on the Tristate Data bus lines.  Here are the images from two of the attempts I have made - one using the Generic Tri contrller and the other using a VHDL with Avalon Slave.  At present I do not have a ram chip installed I just want to see the data lines move on my scope.  I haven't put the instruction line onto the RAM for this reason - and so I'm running the etst program from internal ram.   Any ideas welcome. Am I running into problems because I have this all in a schematic whereas most examples seem to stop at the system level?  Can I test the ram lines using the COmmand console without having a ram installed?

[Altera_Forum]

Here are the files.

[Altera_Forum]

I am trying to get a 512k x 8 bit to work hence the bus split at the output. I am aware that there are issues with the way in which the writes occur and enabling but without fixing the data llines issue means I haven't investigated these issues any further.

[Altera_Forum]

Would I be better reverting to an earlier version of the Quartus software? 

  - most of the examples which people have got running are based on SOPC not Qsys.   Is there a problem with this 'conversion' that Qsys applies on some of the older components?

[Altera_Forum]

The program I am using uses pointers to write to the memory - am I having a similar problem 

to this thread?  http://www.alteraforum.com/forum/showthread.php?t=37171  my code:  unsigned char *buffer = (unsigned char *) 0x80000;  while(1)  {  /* Write data to memory */  for( i = 0; i <10000 ; i++ ) {  buffer = 0xff;  buffer = 0x00;  }  }

[Altera_Forum]

are these warnings significant: 

 Info (12130): Elaborated megafunction instantiation "LPM_BUSTRI:inst24" Info (12133): Instantiated megafunction "LPM_BUSTRI:inst24" with the following parameter:  Info (12134): Parameter "LPM_WIDTH" = "8" Warning (12000): Port "tristate_conduit_bridge_0_out_tcm_byteenable_n_out" in macrofunction "inst" has no range declared,the Quartus II software will connect the port to pin "tristate_conduit_bridge_0_out_tcm_byteenable_n_out[0]" because the pin is a member of a single bit bus with the same name as the port Warning (12000): Port "tristate_conduit_bridge_0_out_tcm_chipselect_n_out" in macrofunction "inst" has no range declared,the Quartus II software will connect the port to pin "tristate_conduit_bridge_0_out_tcm_chipselect_n_out[0]" because the pin is a member of a single bit bus with the same name as the port Warning (12000): Port "tristate_conduit_bridge_0_out_tcm_outputenable_n_out" in macrofunction "inst" has no range declared,the Quartus II software will connect the port to pin "tristate_conduit_bridge_0_out_tcm_outputenable_n_out[0]" because the pin is a member of a single bit bus with the same name as the port Warning (12000): Port "tristate_conduit_bridge_0_out_tcm_read_n_out" in macrofunction "inst" has no range declared,the Quartus II software will connect the port to pin "tristate_conduit_bridge_0_out_tcm_read_n_out[0]" because the pin is a member of a single bit bus with the same name as the port Warning (12000): Port "tristate_conduit_bridge_0_out_tcm_write_n_out" in macrofunction "inst" has no range declared,the Quartus II software will connect the port to pin "tristate_conduit_bridge_0_out_tcm_write_n_out[0]" because the pin is a member of a single bit bus with the same name as the port Warning (12241): 4 hierarchies have connectivity warnings - see the Connectivity Checks report folder Info (13000): Registers with preset signals will power-up high Info (13003): DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back

[Altera_Forum]

Well it looks like what was doing me in the last three days was the cached memory... 

 use IOWR bypasses the cache and all of a sudden bits appeared on the bus.  IOWR is in io.h not stdio.h