Logic use of "Altera Remote Update IP Core"

Programmable Devices

CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers

Logic use of "Altera Remote Update IP Core"

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I have a design running on a Cyclone IV with a self-made FW update block. I now would like to switch to the "Altera Remote Update IP Core", since this core has the possibility to survive a power down during FW update. My problem is my FPGA is quite full (80% of logic).

Is there anywhere an example with the "Altera Remote Update IP Core" for a Cyclone IV? The example I found was with a Cyclone V and the integrated Remote Update was some kind of Altera-self-made-block instead of the normal QSYS block...

Or can somebody tell me how much logic this Remote Update will need? Then I can calculate if it makes sense to implement it.

Best regards

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