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Altera_Forum
Honored Contributor I
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Quartus IP catalog On Chip Mem does not provide waitrequest

Am I missing something? The IP Catalog for generating verilog does not provide a waitrequest signal?? 

 

In real life, on-chip mem will assert backpressure with a waitrequest. However, the IP at IP Catalog>On Chip Memory> 2-Port RAM does not allow configuration for one or generate the signals and logic. Am I missing something? I assume I'll have to build it in....I realize this small thing was what was throwing off my synthesized application.
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Altera_Forum
Honored Contributor I
42 Views

 

--- Quote Start ---  

Am I missing something? The IP Catalog for generating verilog does not provide a waitrequest signal?? 

 

in real life, on-chip mem will assert backpressure with a waitrequest. However, the IP at IP Catalog>On Chip Memory> 2-Port RAM does not allow configuration for one or generate the signals and logic. Am I missing something? I assume I'll have to build it in....I realize this small thing was what was throwing off my synthesized application. 

--- Quote End ---  

 

 

Since when? On chip FPGA memory is implemented as SRAM blocks, so it is purely a slave that responds after a fixed delay. There is typically no waitrequest handshake provided. 

 

waitrequest I believe is specific to the Avalon bus interface spec, so you would need to find an IP block that is implemented for the Avalon bus. 

 

Can you give an example of ON CHIP FPGA memory that has such a feature? I could see that an SDRAM controller (which has embedded refresh controller) and has a variable response delay could provide such a response handshake, but this would be controlling external SDRAM devices.
Altera_Forum
Honored Contributor I
42 Views

ak6dn, 

 

Hi ak6dn, I want to be able to attach memory with either 1 or 2 cycle delays. My problem originates from my original post, where ModelSim produces unpredictable memory access delays. In the (small) image of that post, you can see sometimes the RAM would have a 1-cycle delay and sometimes a 2-cycle delay, which is unacceptable: 

https://www.alteraforum.com/forum/showthread.php?t=55093  

I attached an image of the waitrequest signal observed in SignalTap when Qsys IP altera_avalon_onchip_memory2 is synthesized. I am wanting the simulation model control flow to at least behave like the synthesized product. 

 

[SOLUTION!!] 

Since generating RAM with IP Catalog>On Chip Memory> 2-Port RAM provided no wiatrequest, so I used the below Verilog to recreate the signal:  

 

`define READ_LATENCY 4'd2 // Supports up to 15-cycle latency reg wr_cnt_a, wr_cnt_b; assign waitrq_a = (wr_cnt_a == 0) ? rden_a : (wr_cnt_a == `READ_LATENCY) ? 1'b0 : 1'b1; assign waitrq_b = (wr_cnt_b == 0) ? rden_b : (wr_cnt_b == `READ_LATENCY) ? 1'b0 : 1'b1; always @ (posedge clock or posedge aclr) begin if(aclr) begin wr_cnt_a <= 4'd0; wr_cnt_b <= 4'd0; end else begin wr_cnt_a <= waitrq_a ? wr_cnt_a + 4'b1 : 4'b0; $display("wr:%u cnt:%u", waitrq_a, wr_cnt_a); wr_cnt_b <= waitrq_b ? wr_cnt_b + 4'b1 : 4'b0; end end  

 

 

I attached an example 2-port on-chip RAM Verilog file that generates a waitrequest signal with a configurable read latency from 1-15. As well as the new ModelSim signals that show it working. 

 

Hopefully this helps anyone else looking to simulate the waitrequest signal for the Altera Avalon interface.
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