Looking for Cyclone V Triple Speed Ethernet (TSE) SGMII Example Design Files

[TuckerZ]

Hello, 

I am looking for example design files for adapting to SGMII using Intel's Triple Speed Ethernet (TSE) in Cyclone V devices. I was reading Application Note 796 (Section 4.5.1.2.4) where it said to refer to the example design to see an example of adapting the HPS's EMAC to SGMII. The example design is on RocketBoard.  It contains a broken link to the FPGA files (cv_soc_sgmii_ed.tar.gz) of the example design. Does anyone have or know where to find these files? Has this been uploaded somewhere else? Is there someone or someplace else I should ask this question to? I want to specifically see what the SDC file looks like. 

Thank you, 

TuckerZ

[JingyangTeh_Altera]

Hi

The example are generated using the Quartus 14.2 version which is very old.

Running it in a newer version could cause some migration issue.

I have attached the project here for your reference.

Regards

Jingyang, Teh

[TuckerZ]

Did you attached the project? I can't see it.

[JingyangTeh_Altera · Accepted solution]

Hi

I will try to upload the design again.

Could you see it now?

Regards

Jingyang, Teh

[TuckerZ]

Yes, I can view the files. Thank you!

[JingyangTeh_Altera]

Hi

I’m glad that your question has been addressed, I will now transition this thread to community support. If you have a new question, Please login to ‘https://supporttickets.intel.com/s/?language=en_US’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.

Regards

Jingyang, Teh