Looking for FPGA that can have FF and shift register that can clock at 1GHz

[Altera_Forum]

Hi 

I designed with Apex 10 years ago. I am designing circuit that use FF, latches, 14 bit adders, and some simple combination logic that can run on a synchronous 1GHz clock. I don't need any fancy processor, DSP etc, just simple circuit even the old MAX Plus can do, but just need to run at 1GHz clocking.  Can you suggest the fastest and latest family FPGA I can look into?  I programmed with the Quartus 10 years ago, what is the latest version for programming? Is it similar with the original Quartus I learned before?  Is there any free simulation program?  Thanks  Alan

[Altera_Forum]

I am looking for deserializer, I don't think Ti even have a part that can use external serial data clock. Everyone just have the serial data input and use PLL to lock onto the data. so far, other than 100EP455, the only other I can find is MAX3885. If you know of any other ones, please let me know. 

 Thanks

[Altera_Forum]

--- Quote Start ---  I am looking for deserializer, I don't think Ti even have a part that can use external serial data clock. Everyone just have the serial data input and use PLL to lock onto the data. so far, other than 100EP455, the only other I can find is MAX3885. If you know of any other ones, please let me know.   --- Quote End ---   These are pretty much the same ones that I found too.   You should go and create the VHDL/Verilog to describe the design using 1Gbps LVDS channels. Then create a simulation with a realistic input signal and see if it works ok. There may be something you've missed, and that 1Gbps is not fast enough. If that is the case, then you'd need to look at using the FPGA SERDES channels.   Look in the Arria device overview, there are parts with 36 SERDES transceivers, and their LVDS channels operate at up to 1.6Gbps (the LVDS data rate might be device speed specific - read the data sheet).  Cheers, Dave

[Altera_Forum]

Thanks Dave 

 I never expect one FPGA can get into thousands of dollars!!! I would like to try $300 or below. I downloaded Arria GX, Arria II and Arria V. which one is better for my application? Of cause I would like to have as many 1GHz SERDES channel as possible.   Anyone of these have Flip Flops that can be clocked at 1GHz? If these don't have it, what is the lowest cost FPGA that has 1GHz flip flop?  Thanks

[Altera_Forum]

I went on Altera site and check against Digikey. Looks like the only one that has 18 serial channel is Arria V 5AGXMA5G4F31C4N that is $793. All the others are way over $1000. Can this one work?

[Altera_Forum]

--- Quote Start ---   Can this one work?   --- Quote End ---   Sure, lots of them can work, but you need to *STOP* looking at the prices and *IMPLEMENT* a design using the 1Gbps LVDS channels.  Once you have *CONFIRMED* that 1Gbps LVDS works for your application, then you can look at the Arria series devices that support that LVDS rate. They will be lower cost than the SERDES parts.  However, if your simulations with realistic signals feeding into 1Gbps LVDS show you *CANNOT* use 1Gbps, but that you need to use a faster sample rate, then you have to look at using the SERDES devices in lock-to-data (synchronous) mode.  You've got to learn how to use the LVDS IP cores, and then perhaps the SERDES IP cores. Start with the LVDS IP cores, they are easier.  Cheers, Dave

[Altera_Forum]

--- Quote Start ---   I downloaded Arria GX, Arria II and Arria V.   --- Quote End ---   I have no idea. I have not read the data sheets. I looked at the Arria V data sheet and confirmed that its LVDS operate at 1Gbps. Its up to you to do the work to look at the other data sheets.    --- Quote Start ---   Anyone of these have Flip Flops that can be clocked at 1GHz?   --- Quote End ---   A 1Gbps LVDS receiver is a serial-to-parallel converter operating at 1GHz clock rate. It is a hard IP block in the FPGA I/O core. But I have already explained that. You should have taken the time to read the Stratix V handbook LVDS section.  Cheers, Dave

[Altera_Forum]

Thanks, I read the LVDS section first.

[Altera_Forum]

--- Quote Start ---  Thanks, I read the LVDS section first.  --- Quote End ---   Excellent :)  Then create an instance of the component and try to simulate it. The LVDS IP core User Guide might have a simulation example associated with it.  Yeah, there is, go here  https://www.altera.com/support/literature/lit-ug.html  and scroll down to "LVDS SERDES Transmitter / Receiver (ALTLVDS_TX and ALTLVDS_RX) IP Core User Guide". There's a bunch of example designs.  There is no guarantee that any of these examples is good, but at least its a start :)  Cheers, Dave

[Altera_Forum]

Hi Dave 

Hate to keep going around, I read the Clocks in Chapter 4 and I/O of chapter 5 in the Stratix V manual and I read the datasheet of Stratix V. then I read chapter 1 in LAB, ALM etc that I can have 2 4 input block, a 6 input block and all that. It absolutely did not answer any of my questions and concern. Yes, I learn there are GCLK, RCLK that divided into 4 quadrants, PCLK. I learn all the different standard of input by adjusting the VccIO and VCCPD etal. I learn there are different I/O bank like 3A, 3B, 7A........... I scanned through pages of the Arris II data sheet, same thing. I even scanned through the Stratix design guide.  My basic questions are very basic and simple that can help me in choosing the device:  1) What is Reference clock vs data rate in the I/O 2) Max clock frequency of simple basic FF and register. 3) Tpd from clock to Q. 4) Ts data setup time on D input to rising edge of clock( without worrying about the programmable delay line). 5) Th data hold time of D input from rising edge of clock( without worrying about the programmable delay line). 6) Tpd of simple AND, OR, NAND, NOR gate. 7) Are the FF/registers synchronous reset or level reset. 8) Do the FF/registers have clock enable.  These can be written in one short page and people will know exactly how to design the basic core elements. All you have to do is then talk about how to program to run the clock in GCLK, RCLK or PCLK to control skew and program the setup and hold time with the programmable delay. But the documentation rattling on for hundreds of pages.....................   As I said, I am no expert in FPGA programming. BUT I fixed enough problem left by the supposedly "FPGA engineer", people over threat programming FPGA like software programming. People seems to forget this is real hardware with wires, transistors. I had to fix FPGA programs in the pass written by some "FPGA engineers" on intermittent problems in the system that turn out to be the reset of the FF driven by combination logic. Totally ignore that these are really electrical signal that have propagation delay and can create glitches on the reset line during the transition of the input of the combination logic and reset the FF. This is such an obvious thing that the old school digital designer can spot in a seconds. Believe me, I caught multiple programs like this. fix these and the system became reliable. I can't help by vent the frustration in reading materials from Altera. My experience is the same when I went through MAX and APEX design. Just going around and around.  Sorry to vent.,  Alan.

[Altera_Forum]

--- Quote Start ---   Hate to keep going around   --- Quote End ---   Its ok, try not to get frustrated :)    --- Quote Start ---   My basic questions are very basic and simple that can help me in choosing the device:  1) What is Reference clock vs data rate in the I/O 2) Max clock frequency of simple basic FF and register. 3) Tpd from clock to Q. 4) Ts data setup time on D input to rising edge of clock( without worrying about the programmable delay line). 5) Th data hold time of D input from rising edge of clock( without worrying about the programmable delay line). 6) Tpd of simple AND, OR, NAND, NOR gate. 7) Are the FF/registers synchronous reset or level reset. 8) Do the FF/registers have clock enable.   --- Quote End ---   The LVDS receiver deserializer blocks are hard-IP, i.e., they are built into the I/O elements of the FPGA. That is why they can run at 1Gbps, while the fabric operates at say 1:4 250MHz or 1:8 125MHz.  In FPGAs you do not perform manual timing analysis. There are just too many variables. You have to create a design in Quartus, apply timing constraints, such as the clock frequencies, and then use the TimeQuest tool to perform the timing analysis for you.  Quartus knows what the timing requirements are from the LVDS hard-IP to the FPGA fabric, so you just let it do its job.    --- Quote Start ---   As I said, I am no expert in FPGA programming. BUT I fixed enough problem left by the supposedly "FPGA engineer", people over threat programming FPGA like software programming. People seems to forget this is real hardware with wires, transistors. I had to fix FPGA programs in the pass written by some "FPGA engineers" on intermittent problems in the system that turn out to be the reset of the FF driven by combination logic. Totally ignore that these are really electrical signal that have propagation delay and can create glitches on the reset line during the transition of the input of the combination logic and reset the FF. This is such an obvious thing that the old school digital designer can spot in a seconds. Believe me, I caught multiple programs like this. fix these and the system became reliable. I can't help by vent the frustration in reading materials from Altera.   --- Quote End ---   Read the Quartus II handbook. Altera does try to provide recommended design procedures, eg., asynchronous reset assertion with synchronous deassertion. But alas, not everyone takes the time to read or learn from the older wiser engineers :)    --- Quote Start ---   Sorry to vent.,   --- Quote End ---   Don't sweat it. Just follow my recommendation.  Create an ALTLVDS_RX instance and get it to work. You can create one instance with an internal PLL, and then create another instance with an external PLL and separately instantiate the PLL. You could then use the ALTPLL_RECONFIG interface to sweep the phase of the PLL and do all sorts of things. Start out simple though, just get the ALTLVDS_RX to work. The example designs in the IP guide should be good enough to get started. If they are not, let me know, and I'll take a look and make a nicer one.  Cheers, Dave

[Altera_Forum]

Thanks Dave 

I have worked on the design quite a bit to slow down the speed requirements. I can get away with pipeline register with NO LOGIC in between clocking at 250MHz. This means from clock to Q of the first register driving the D input of the second register fulfilling the setup time of the D input has to be less than or equal to 4nS. But I need at least 300 DFF running at 250MHz. My new design do not even need Transceivers ( cost!!)  What is the slowest/cheapest FPGA family I can use? Can I get down to MAX or Apex? Or I still need to go up to Arris or Cyclone?  Thanks  Alan

[Altera_Forum]

--- Quote Start ---   I have worked on the design quite a bit to slow down the speed requirements. I can get away with pipeline register with NO LOGIC in between clocking at 250MHz.   --- Quote End ---   Is this external to the FPGA? If that is the case and you generate 250MHz LVDS signals, the FPGA/CPLD I/O cells can operate at 125MHz double-data-rate. Most devices can handle that.    --- Quote Start ---   This means from clock to Q of the first register driving the D input of the second register fulfilling the setup time of the D input has to be less than or equal to 4nS. But I need at least 300 DFF running at 250MHz.   --- Quote End ---   300 registers at 250MHz or 600 registers at 125MHz should be no problem in several different devices. I've got designs in MAX II devices operating at 125MHz. I don't think MAX II has DDR registers. Check out the MAX 10 family, they might. Also look at the Cyclone.     --- Quote Start ---   What is the slowest/cheapest FPGA family I can use? Can I get down to MAX or Apex? Or I still need to go up to Arris or Cyclone?  --- Quote End ---   Every time you come up with a logic scheme, you need to come up with an HDL design. The timing analysis needs a device part number, and that part number needs a speed grade. Try synthesizing your logic in several different devices and speed grades, and you'll see which ones can operate with your timing requirements.  Cheers, Dave

[Altera_Forum]

Thanks Dave 

 I have a question about the double data rate. I assume you are talking about triggering registers on both edges of the clock so a 125MHz can clock data at rate of 250MHz.  BUT, it is really not the frequency of the clock that matter alone. For example, you clock at 250MHz with only single edge, the period between the two edges is 4nS. You run at 125MHz but clock at both edges, your period between the two edges is still 4nS!!! You are not buying anything. Not to mention you can run into duty cycle problem that stretch one side and you have less than 4nS on the other side. That is even worst.  Let's for the sake of talking, say you drive a simple shift register with both edge, so you clock one register with +ve edge, and the following register with -ve edge etc. So a 125MHz clock will shift the register at 250MHz rate if it is triggered by a single edge. BUT you are not gaining anything as the speed is limited by clock to Q plus the data setup time of the next register. You still only have 4nS total for that....At best if you have true 50% duty cycle.  That's the reason I never design with clocking with both edges ever. I just don't see any advantage of this. Am I missing something?  that's the reason I keep asking about the data setup time and hold time because that's what really govern the speed.  Thanks  Alan

[Altera_Forum]

Hi Dave 

 Attached is the schematic of my new design and also the timing diagram. As you can see, it takes over 300 DFF to lower the speed from 1nS to 5nS data rate. I never understand how people talk about it's easy, you just demux 1:5 to reduce from 1GHz data to 200MHz ( 1nS period to 5nS period). CLK[0..4] are 5 phase clock that are offset by 1nS from each other.  I see people talk about using a select strobe and just strobe the 1GHz data into 5 different 16bit register or a 5 phase clock like my design, then strobe the data all into the second set of register at the last strobe of the first register. So theoretically you only need 10 of 16bit register or 160 DFF to do the job.  The 3rd attached image is a typical 1:5 demux to slow the clock from 1GHz to 200MHz. I use the same 5 phase clock like my design. If you look at it more carefully, true the first register have 4nS for data to settle before strobe into the second set of registers. The second register has only 3nS as it was being strobe 1nS later than the first register. this goes on. The 4th register has only 1nS before the output has to be strobe to the second set of register!!! So the forth register has to actually work at equal to 1GHz clock rate that the clock to Q plus the data setup time to the second set of register has to be better than 1nS!!!  In my design, I have to have 3 steps to guaranty have have 4nS minimum between the pipeline registers. That's the reason I asked about 250MHz (4nS) instead of design of 200MHz. There is no free ride, AND that's the reason I put so much thoughts on the timing, setup and hold time and draw out the timing diagram. I have seen too too many so call digital or FPGA engineers mess up in the design and cost a whole lot more time to troubleshoot than to just sit down for a few hours and draw out and take care of the timing issue.  Again, I still believe this is real circuit, you cannot think of it as programming.  Alan

[Altera_Forum]

Hi Alan, 

 This is an Altera FPGA design forum. You need to start showing some designs that use an Altera FPGA. Try using the ALTLVDS_RX component and the DDR registers in the IOE. Until you do that you have completely missed the advice I have been giving.  Cheers, Dave

[Altera_Forum]

For coincidence detection, you can also use a slower clock with different phase shifts. 

For 1 ns resolution for instance, you can use a 125 MHz clock (8 ns period) with phase shifts @ 0, 45, 90, 135, 180, 225, 270, & 315 degree. Then you can sketch a plan to detect coincidence within 1 ns resolution using 8 copies of a circuit, operating at phase shifted versions of a slower clock. For SerDes capable FPGAs, you can use from Cyclone to Stratix. Nearly all the modern FPGAs have SerDes capabilities @ 1GHz.

[Altera_Forum]

I think this application sounds like TOF or PET. You need to implement TDC inside FPGA, there are several guys talking about this topic:http://www.alteraforum.com/forum/showthread.php?t=51960