Looking for a Simulator that supports SV Assertions

[Altera_Forum]

Hello, I'm looking for a simulator that supports System Verilog Assertions and have narrowed by search down to Aldec and Mentor.  

 Mentor's ModelSim DE is a little more expensive then Aldec's tools.   I really would like to be able to do all the SV Verification stuff but that increases the price, so I thought it may be cheaper just to be able to do SV Assertions. I'm looking at Aldec's DE, PE and LV simulators. Can anyone comment on these simulators or can suggest another vendor?  Thanks, joe

[Altera_Forum]

Hello, I wanted to give some more information. In the hardware development branchI work in we have been using the simulator built-in the Quartus tool. We usually run a simulation that does a few reads and writes and then call the design good, therefor our sims are usually short.  

 Some in the branch are switching to ModelSim that comes with the Quartus subscription. I'm learning about testbenches and from what I have read you can set up the test bench to run thousands of read/write transactions and have the test bench verify each transactions. This appeals to me because I won't have to scroll through waveforms trying to decipher if these are working.   I've been reading about the SystemVerilog Verfication model and was wondering if I only want to automate my testing will SystemVerilog assertions be sufficient? This would reduce the cost of the simulator. To implement everything described in SV for Verification drives up the cost of a simulator.   Thanks, joe

[Altera_Forum]

--- Quote Start ---  . I'm learning about testbenches and from what I have read you can set up the test bench to run thousands of read/write transactions and have the test bench verify each transactions. This appeals to me because I won't have to scroll through waveforms trying to decipher if these are working.     --- Quote End ---    That's precisely what we advice to our customers - whatever you "eyeball" in waveform, capture them using assertions (SVA or PSL). This would help in automating checks during simulations.    --- Quote Start ---   I've been reading about the SystemVerilog Verfication model and was wondering if I only want to automate my testing will SystemVerilog assertions be sufficient?    --- Quote End ---    Depends on what you mean by "testing" - the "checker" portion of it to a large extent can be captured with Assertions. For generating intellignet stimulus and modeling reusable testbenches you will require more capable features from SystemVerilog such as classes, constraints, functional coverage etc.  I recommend you read some of the advanced verification challenges in forums like verificationguild.com, cvcblr.com/blog etc. But since you are just starting to explore, it will be a good idea to get going with SVA/PSL and then take up full SV once you see value.     --- Quote Start ---   This would reduce the cost of the simulator. To implement everything described in SV for Verification drives up the cost of a simulator.   Thanks, joe  --- Quote End ---    In general YES, but given the availability of more tools with SV support, it is becoming more competitive for EDA vendors thereby bringing down the cost. If you have good negotiator you may be able to get few SVA-enabled tools and few full-SV enabled tools.  Good Luck Srini cvcblr.com/blog