Using System Verilog Assertions

[Altera_Forum]

Hello, I've seen a few books on System Verilog Verification using assertions and was wondering if many people are using assertions in their FPGA development? My co-worker says it can be a lot of typing. Is it worth spending money for a simulation tool that supports assertions? 

 Thanks, joe

[Altera_Forum]

I think it actually saves typing :) 

All the books that I've read also come to that conclusion. But I'm not using it because Modelsim DE is too expensive for my company at the moment.

[Altera_Forum]

--- Quote Start ---  I think it actually saves typing :) All the books that I've read also come to that conclusion. But I'm not using it because Modelsim DE is too expensive for my company at the moment.  --- Quote End ---   Actually, assertions help in clarifying the requirements, the design review process, and the speed of debugging errors. In addition, it can provide information about coverage. So the time lost in typing is significantly gained in getting accuracy in the modeling of the design (because the assertions clarify the requirements), and in the verification of the design. See my paper on checkers at my site systemverilog.us/DvCon2010 Even though the paper addresses IEEE 1800-2009 checkers, consider the assertions aspect of the design and the value of those assertions in the design and verification process.  -------------------------------------------------------------------------- Ben Cohen (831) 345-1759  systemverilog.us/  * SystemVerilog Assertions Handbook, 2nd Edition, 2010 ISBN 878-0-9705394-8-7 * A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5 * Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0  * Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 0-9705394-2-8  * Component Design by Example, 2001 ISBN 0-9705394-0-1 * VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1 * VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115 --------------------------------------------------------------------------

[Altera_Forum]

Thanks Ben! I had the same thoughts; it is just a matter of convincing my co-workers to adopt the practice of using assertions and other verification tools. 

 Thanks, joe

[Altera_Forum]

--- Quote Start ---  Thanks Ben! I had the same thoughts; it is just a matter of convincing my co-workers to adopt the practice of using assertions and other verification tools.   --- Quote End ---  A few comments:  1. assertion-based verification should be adopted by all involved in the design and verification process. Having partial adoption weakens the process.  2. I put the 1st ten pages of our book at systemverilog.us/abv_pg1to10.pdf It explains why assertion-based verification is very important.  3. I now have an Indian edition on our SystemVerilog Assertions Handbook, 2nd Edition book available through Srinivasan Venkataramanan. Contact him at cvcblr.com Srini also provides training and design services. See his site for details.  4. For training in the US, Stuart Sutherland at sutherland-hdl.com provides SVA training and a copy of our SystemVerilog Assertions Handbook, 2nd Edition book is handed out as part of the course.  -------------------------------------------------------------------------- Ben Cohen (831) 345-1759  systemverilog.us/ ben at ystemverilog.us  * SystemVerilog Assertions Handbook, 2nd Edition, 2010 ISBN 878-0-9705394-8-7 * A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5 * Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0  * Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 0-9705394-2-8  * Component Design by Example, 2001 ISBN 0-9705394-0-1 * VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1 * VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115 --------------------------------------------------------------------------

[Altera_Forum]

Thanks Ben for the plug-ins to cvcblr.com Recently I presented at FPGACamp Bangalore evnt on SystemVerilog for FPGA design & verification, see: 

 Search in Google for "FPGACamp Bangalore systemverilog" (Am unable to post URL links in this forum as of now)  I will be glad to share the slides, contact us via cvcblr.com (About Us page has a contact form).  IN Bangalore we have successfully trained several FPGA engineers to adopt modern design & verification methodologies using PSL/SystemVerilog Assertions and even VMM. We have seen that Active-HDL fits their bill smoothly to explore SVA/PSL Recently Mentor released their DE version with similar features. So you have multiple choice!  Regards Srini cvcblr.com/blog