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Altera_Forum
Honored Contributor I
981 Views

MAX 10 FPGA power-on/configuration error

I have a custom board with a 10M25SAE144xxx part that I am trying to bring up, but the device seems to be failing configuration at power-on. This is a single-supply device, and power is applied through an Enperion +3.3V regulator. 

 

+3.3V is present at all power pins; voltage verified to all VCC_ONE, VCCA, and VCCIO pins. Using an oscilloscope, the voltage looks clean and ramps up in less than 1.4 ms. 

 

These pins are pulled to +3.3V through 10K ohm resistors: 

nCONFIG 

nSTATUS 

CONF_DONE 

DEV_CLRn 

JTAGEN 

(with power off I have determined that these pins do have a 10K ohm path to the +3.3V rail) 

 

This pin is connected to ground through a 10K ohm resistor: 

CONFIG_SEL 

 

After power-up, nSTATUS and CONF_DONE remain at 0V, never appearing to configure and pull up to +3.3V as expected. nCONFIG stays at +3.3V. 

 

This design was done using these documents as reference: 

"MAX 10 FPGA Configuration User Guide" 

"MAX 10 FPGA Device Family Pin Connection Guidelines" 

"Intel MAX 10 FPGA Design Guidelines" 

 

 

 

Are there any other pins that need to be set for configuration? 

 

Are there any other indicators that I can look at to determine what the configuration error might be? 

 

Is there anything else I can test to diagnose this? 

 

Is there any way to determine if I have a bad chip? How common is this?
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6 Replies
Altera_Forum
Honored Contributor I
118 Views

Did you ever resolve this issue. I am experiencing similar issues.

Altera_Forum
Honored Contributor I
118 Views

I did get this resolved by replacing the part. On the original part we went over every pin (all 144 of them) re-flowing solder, checking continuity, checking voltages, and making sure there were no solder bridges to adjacent pins, but everything checked out and it still did not work. We replaced the part, assuming that it was bad, and the replacement part worked. 

 

One thing I had been confused about was when I should expect the nSTATUS and CONF_DONE pins would go high. To me the documentation was not clear, so I had been thinking that they should go high (through the pull-up resistors) shortly after power was applied. I found that they would actually do this after connecting with the JTAG programmer and configuring/loading the .sof file. I'm not sure when during this process that happens, but noticed it when I was able to finally get the programmer to recognize the part and then I did the download and checked the pin voltages afterward.
Altera_Forum
Honored Contributor I
118 Views

CONF_DONE won't go high until you've successfully configured the device. 

 

IIRC, without a valid image in the flash you'll see nSTATUS go high after the PoR time, and then go low again when the config fails (assuming nCONFIG is high so as to allow the configuration to start). Possibly with a completely blank device it's so quick you can't see it - I'll try to have a look next time I have a blank device on hand.
Altera_Forum
Honored Contributor I
118 Views

I managed to resolve the issue by placing a weak pull-up (10K) resistor (to 3.3V) on the CONF_DONE pin.

Altera_Forum
Honored Contributor I
118 Views

 

--- Quote Start ---  

I managed to resolve the issue by placing a weak pull-up (10K) resistor (to 3.3V) on the CONF_DONE pin. 

--- Quote End ---  

 

 

On Altera devices conf_done and nstatus are bidirectional, open-drain pins. They can ONLY drive low. A pullup (10K recommended) to VCCPGM (usually +3.3V) is required, not optional.
Altera_Forum
Honored Contributor I
118 Views

Hi plewis, 

 

Regarding your comment.. 

"i did get this resolved by replacing the part"  

really implies that 'bad FPGAs' are making past Altera / Intel's quality check process and making to the market?! This is quite troubling.. 

I am right now facing a similar Configuration problem, where the only path left seems to be, is to try a different board / FPGA chip.  

 

Also from another forum post (https://www.alteraforum.com/forum/showthread.php?t=56631), it appears that JTAG configuration problems are erratic and unpredictable.  

The discussion in the referred post raises troubling questions about the 'reliability' of the JTAG configuration, which one expects to be really robust, considering it's importance.
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