MAX 10 JTAG programming

[Dan_Suciu]

Hello,

I am trying to implement a uC based JTAG re-programming of a MAX10  10M16SAE144 chip by using a .svf file (when no physical access to the JTAG connector is available in the field).

I generated the .svf file using Quartus Prime Lite Edition Programmer and I could find in MAX 10 documentation most of the ISP instructions codes generated in the .svf file, except for: x307,  x3F2 and x3F4.  Anyone knows what are those instructions doing?

I have occasional errors in the verification process and I hope to correct them by erasing and re-writing those pages only.

The only instruction code I could find about erasing is x2F2, but it is not clear to me, if that will erase only the page starting at the address provided with the earlier ISC_ADDRESS_SHIFT instruction, or all subsequent pages.

Instruction x3F2 seems to be a general ERASE.

There is any document describing all ISP instructions available to the user?

Thank you,

Dan

[Mikexx]

I know I am not directly answering your question, but ..........

I was wondering if you were reliant on the JTAG pullups for a logic high, or if you're using push-pull MCU outputs. I would strongly recommend using push-pull for the clock if nothing else.

If you're already doing this then I can't explain the issues you're seeing.

[Dan_Suciu]

Hello Mike,

Thank you for your reply. Definitely the signals rise/fall time  and levels are very important. 

I have the micro-controller with pins outputs push/pull mode and the signals are shorter rise/fall time (approx. 10ns 10% to 90%), compared with USB Blaster used to program .pof file over the same JTAG interface.

The clock frequency I use is lower than used in Blaster, and the calculated delays when generating .svf file, should be longer than required.

I was able to generate a version of the .svf file doing only erase and verify the blank memory using the Blaster.

Thank you anyway,

Dan

[NurAiman_M_Intel]

Hi,

Apologize for the delay in response.

Do you still require further assistance for this case?

I assume you have refer to below page?

https://www.intel.com/content/www/us/en/docs/programmable/683865/current/isp-and-real-time-isp-instructions.html

Let me know the update

Regards,

Aiman

[Dan_Suciu]

Hello Aiman,

Thank you for reaching out regarding my  issues using svf file.

In the mean time, I was able to identify the problem causing occasional miss writings. It was the serial communication from the computer running a JAVA program who reads the svf file and generates serial commands transmitted to my uC which will process them into JTAG signals for the TAP controller in MAX10. The serial commands occasionally were not contiguous, having gaps between characters, larger than the timeout I programed in the uC for detecting the end of the message, hence the uC was rejecting the command and skipped to the next one.

The problem is fixed now and I was able to load the FW in the FPGA from the svf file and it works.

I am working now to improve the programming time which is very long.

I still need help with some ISP instruction codes I could not find info about:

x002, x003, x004, x307,  x3F2 and x3F4.

I can see they are used in the generated svf file but I could not find description about them. The other codes as the one in the link you sent me, are clear.

If you can send me some info about those instruction codes would be a big help.

Thank you,

Dan

[NurAiman_M_Intel]

Hi,

Looks like x002, x003, x004, x307, x3F2 and x3F4 is not there in the Max 10 userguide.

Let me check this internally and I will revert back to you again.

Regards,

Aiman

[NurAiman_M_Intel]

Hi,

Can you provide the .svf file?

Regards,

Aiman

[NurAiman_M_Intel]

Hi,

Any update for the .svf file?

Regards,

Aiman

[Dan_Suciu]

Hello Aiman,

I was out for few days, hence the delayed response.

I cannot give you the whole svf file but I can do few excerpts where some of the undocumented codes are located:

!Max 10 DSM Clear
!
SIR 10 TDI (203);
RUNTEST 8 TCK;
SDR 23 TDI (000000);
SIR 10 TDI (3F2);
RUNTEST 350003 TCK;

!
!Max 10 DSM Verify
!
SIR 10 TDI (307);
RUNTEST 8 TCK;
SDR 1 TDI (0) TDO (1) MASK (1);

!
!Max 10 Program CFM1
!
SIR 10 TDI (203);
RUNTEST 8 TCK;
SDR 23 TDI (001E80);
SIR 10 TDI (2F4);
RUNTEST 8 TCK;

!
!Max 10 Program Done Bit
!
SIR 10 TDI (203);
RUNTEST 8 TCK;
SDR 23 TDI (440000);
SIR 10 TDI (3F4);
RUNTEST 8 TCK;
SDR 32 TDI (6C48A50F);
RUNTEST 320 TCK;

Again, it is not critical at this point since I was able to program the FPGA, but I found it weird not to find documentation about some of the codes used in the svf file.

Who wrote the programmer conversion function to generate svf file, must have had the information about those codes and their use.

I am not interested in any factory reserved instruction codes, but only the codes generated automatically by the Quartus Programmer.

Thank you again for your support,

Dan

[NurAiman_M_Intel]

Hi Dan,

Update from internal team, all the codes you asked is private to Altera only. However I am trying to find a solution for your queries. Will update you soon.

Regards,

Aiman

[Dan_Suciu]

Thank you Aiman.

[NurAiman_M_Intel]

Hi,

We look at MAX10's JTAG architecture and the granularity of the flash erase for ISC_ERASE instriuction is per flash partition not pages. Is there any concern to do the flash erase per partition rather than pages?  

Regards,

Aiman