Hello,Moving small part of Cyclone 5 project over to a MAX 10. Has NIOS and of course the UFM for code storage. TimeQuest gives me this error as an unconstrained clock: inst6|altera_onchip_flash:flash|altera_onchip_flash_avmm_data_controller:avmm_data_controller|flash_se_neg_reg Base Unconstrained TimeQuest reports no other errors. I have no idea what to do as I always assumed the NIOS SDC file would handle all things timing (The NIOS QIP file does specify three SDC files, and one is for the "altera_onchip_flash.sdc" Thanks.
Hello sstrell,I have one input clock into the entire design. It is constrained. The issue I pointed out is a clock within the NIOS processor isn't constrained. More digging shows other engineers with the same problem: http://www.alteraforum.com/forum/showthread.php?t=52351&p=215359#post215359 And the answer is that it still isn't fixed: "To keep you informed, I got in touch with an Altera AE and he told me that problem was found as bug in the RTL code of the Flashaccelerator Wait Request and the bug should be fixed in a future version of Quartus. Quartus 16.0.2 doesn't contain the bugfix yet." So, Altera - what is the recommend workaround? TIA