Hello, i had some code in my quartus project which read data from nios depend on writedata. So, programmer is always faild at 87% or 88%. But when i change all integer types to reg (reg popFlag, reg fitFlag, reg rFlag, reg iPop, reg iFit), programmer is succesfull. What are differents between reg and integer or what i do wrong?:(. Sorry, but i am new in verylog.integer popFlag = 0; integer fitFlag = 0; integer rFlag = 0; integer iPop = 0; integer iFit = 0; always @(posedge clk) begin if(write == 1 && writedata == 0) begin popFlag = 1; end if(write == 1 && writedata == 1) begin popFlag = 0; fitFlag = 1; end if(write == 1 && writedata == 2) begin fitFlag = 0; rFlag = 1; end if(write == 1 && popFlag == 1) begin if(iPop < 30) begin pop[iPop] = writedata[15:0]; end iPop = iPop + 1; end if(write == 1 && fitFlag == 1) begin if(iFit < 30) begin fitness[iFit] = writedata[15:0]; end iFit = iFit + 1; end if(write == 1 && rFlag == 1) begin randonValue = writedata[15:0]; end if(read == 1) begin rFlag = 0; iPop = 0; iFit = 0; end end
The programmer fails or do you mean the compiler fails when compiling the design?Is there a reason why you need to use integer (a signed 32-bit variable data type)? reg is more efficient because it only uses as many bits as needed, assuming you specify bit widths (8'h1 for 0x01 for example). You should be initializing these values in the always block with some type of reset signal (instead of initializing them up top) and using non-blocking assignments (<=) instead of blocking assignments (=) if your intent to create clocked registers, which is what this looks like. And is "randonValue" intentional or is that a typo (randomValue)?