Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
21615 Discussions

MAX 10 Power-Up

Altera_Forum
Honored Contributor II
‎09-28-2015 08:11 PM
1,374 Views

Hi everybody. 

 

 

I need the power-up characteristics of the MAX 10. For example, at the MAX II documentation there is the figure attached in which the conditions, to keep the 'user mode' on, are obvious. 

 

 

I would like to know what is the Power On Reset trip level on MAX 10? Once at the user mode, in what voltage level the pins come back to tri-state mode? 

 

I hope someone can help me. 

 

Regards, 

 

Ronan.
Preview file
43 KB
0 Kudos

Link Copied

1 Reply
Altera_Forum
Honored Contributor II
‎10-20-2015 05:08 PM
556 Views

As far I know Altera never publish any device POR trip point voltage level. There is no specific voltage level for tristate pins. Typically tristate pins are high z where it can have either an internal weak pull up or weak pull down settings. Thus if you scope the pins, you might see voltage level is near to high or low level due to the internal weak pull up or pull down resistor.

0 Kudos
Copy link
Reply

Community support is provided Monday to Friday. Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.