MAX 10 dev board with USB Blaster JTAG Issues

[Parkerman1700]

Hello, first time poster here. I have a MAX10 dev board using a 10M50DAF484C6GES. I have been struggling to create just a sample build with the correct pinout that doesn't seems to kill the JTAG interface. Whenever I program the device, it would seem something happens where the FPGA is held in reset, or the JTAG pins are getting scrambled.. or something. I am assuming it's related to incorrect pin constraints.

This is the guide I am using: https://www.mouser.com/datasheet/2/612/ug_max10m50_fpga_dev_kit-1299798.pdf

When I constrain the CPU_RESETn correctly, it does seem to work. It even lets me program it repeatedly, although if I delete it from the list, it can't be discovered on the chain again. But if I constrain the CLK inputs, it seems to make it not work at all. 

I guess I am not quite sure what the JTAG interface even needs on this thing. The example .sof files I am using work fine. 

Any guidance would be great! Thanks

[Fakhrul]

Hi Parkerman1700,

Could you elaborate in details what is the real isssue here? As a start please refer to the following documents:

Intel® MAX® 10 FPGA Configuration User Guide

MAX® 10 FPGA Device Family Pin Connection Guidelines

Regards,

Fakhrul

[Parkerman1700]

Hi! Thanks for getting back. You can mark this as solved, I believe the issue was related to a mismatch of I/O standard on the pin constraints. When the FPGA got programmed, some incorrect I/O standard somewhere was freezing the FPGA and causing the JTAG interface to fail in some way. 

Thanks!

[Fakhrul]

I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.