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Valued Contributor III
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MAX 10: using two ALTPLL

Is it possible using two ALTPLL from one clock source with 10M08D? 

I tried instantiating two PLLs. One has 5 clocks, and the other one has one clock. 

But I got an error message during synthesizing like 

"error (176394): can't fit 2 plls in the device -- only 1 plls are available 

info (176395): location pll_1 cannot be used due to package or device migration constraints" 

 

or this question can be like how can I generate more than 5 clocks from one external source clock? 

 

I'm referring "Fine Resolution Phase Shift" on https://www.altera.com/documentation/mcn1395213337540.html 

 

Thanks.
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Valued Contributor III
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Hi, 

 

1.Have you checked how many PLL available in you device/FPGA? 

This error say it all you device support only 1 but you are using 2 PLL. 

To solve you can change the device in you project. 

 

Let me know if this has helped resolve the issue you are facing or if you need any further assistance. 

 

Best Regards, 

Anand Raj Shankar 

(This message was posted on behalf of Intel Corporation)https://www.alteraforum.com/forum/attachment.php?attachmentid=14886 https://www.alteraforum.com/forum/attachment.php?attachmentid=14887 https://www.alteraforum.com/forum/attachment.php?attachmentid=14888
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Valued Contributor III
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Thanks Anand, 

 

Your are right, only one PLL is available for the chip I am using. There were two PLL from the 10M08 datasheet, but mine is just one. 

 

So now, my question is how can I generate more than 5 clocks when only one PLL is available. 

Is there any way? 

what I want to try is generating 4 phase-shift clocks plus 2 more control clocks. 

Similar one is here. Please look at Figure 2-18 on https://www.altera.com/en_us/pdfs/literature/hb/max-10/m10_handbook.pdf

Please, give me help. 

 

Thanks,
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Valued Contributor III
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Hi, 

 

You can generate max of 5 clocks from one PLL. Not more than 5 clocks. 

Example in Figure 2-18 can be implemented for the 5 clocks. 

Maybe you can design a logic for 1 clock out of 6 clocks(4 phase-shift clocks plus 2 more control clocks) check which one can be implemented easily.  

 

Let me know if this has helped resolve the issue you are facing or if you need any further assistance. 

 

Best Regards, 

Anand Raj Shankar 

(This message was posted on behalf of Intel Corporation)
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