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Altera_Forum
Honored Contributor I
1,481 Views

Problem with FSM on Hardware testing

Hello All, 

 

I have designed Manchester Decoder in System Verilog using 2 always block method. But in testing on hardware, I am analyzing outputs in SignalTap and it is found that after reset one frame is decoded perfectly but after that my FSM is not jumping in any states of FSM. I have five states FSM So after the first frame, my FSM does not jump in any of that five states. So I wanted to know that why this problem is appearing.  

 

I have tried to found solution on net but didn't get it. I hardly got one solution that instead of using 2 process FSM (2 always block FSM) use 1 process FSM (1 always block FSM), I have also tried that but results are same. 

So I hope that I will get some usefull hints or answers from forum experts. 

 

Thank you, 

Tejas Limbasiya
0 Kudos
6 Replies
Altera_Forum
Honored Contributor I
19 Views

Hi, 

 

Output may be latched due output ports handing can you check once. 

1.Have you simulated the code? 

2.Can you provide code? 

Or  

try to use altera quartus template. 

 

Best Regards, 

Anand Raj Shankar 

(This message was posted on behalf of Intel Corporation)
Altera_Forum
Honored Contributor I
19 Views

Hi, 

Double check that all possible transitions out of the state after the first frame is decoded are taken care of. For example, if you have a bunch of If else conditions, or a case statement, make sure you either have a default next state defined, or ensure that each subsection has a next state defined.  

From what you have written about your problem, it looks like it is stuck in the same state . This could be that your default action is to remain in that state till you receive an input to transition to the next state, and it never receives it. Check if the conditions that you are waiting for is a valid one.
Altera_Forum
Honored Contributor I
19 Views

 

--- Quote Start ---  

 

 

 

1.Have you simulated the code? 

(This message was posted on behalf of Intel Corporation) 

--- Quote End ---  

 

thank you sir for your reply. 

Yes I have simulated the code in Quartus 16.1 

 

 

--- Quote Start ---  

 

2.try to use altera quartus template. 

--- Quote End ---  

 

 

You mean to say that I should use the same method as given in Altera Quartus template. ?
Altera_Forum
Honored Contributor I
19 Views

 

--- Quote Start ---  

Hi, 

Double check that all possible transitions out of the state after the first frame are decoded are taken care of. For example, if you have a bunch of If else conditions, or a case statement, make sure you either have a default next state defined, or ensure that each subsection has a next state defined.  

From what you have written about your problem, it looks like it is stuck in the same state . This could be that your default action is to remain in that state till you receive an input to transition to the next state, and it never receives it. Check if the conditions that you are waiting for is a valid one. 

--- Quote End ---  

 

 

thanks for your reply. 

I have checked all possible transitions. If my FSM is stuck in any one state then I can solve out this by modifying some conditions in the if..else loop but here in my case, FSM does not stay in any case of five cases of FSM.  

So if you have faced this kind of problem in past then let me know the reason for that so I can solve out this issue.
Altera_Forum
Honored Contributor I
19 Views

I am a little confused. How many states do you have in total? 

 

--- Quote Start ---  

If my FSM is stuck in any one state then I can solve out this by modifying some conditions in the if..else loop but here in my case, FSM does not stay in any case of five cases of FSM 

--- Quote End ---  

Is it stuck in reset? Do you mean that it jumps through the initial states, but it does not transition to any of the states that you want it to transition to? 

If you are using signal tap to debug, you can add the State machine nodes directly. Right click -> Add state machine nodes -> Select the statemachine. This can give you more information. 

If it works properly in simulation, it could be that some of your input triggers that you provide from the testbench, might have been trimmed in synthesis.  

 

Like Anand Raj said, it would be more helpful if you provide the code.
Altera_Forum
Honored Contributor I
19 Views

yes, divyaganti it is stuck in reset. 

 

But I got a solution for this issue.  

As I have taken input from a gateway, I have used that signal directly in FSM, but now I have taken a flop of that signal and then used that flop in FSM and It starts working. 

 

Again thank you to both of you for your warm replies.