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Difference between "logic" and "bit" data types.

Altera_Forum
Honored Contributor II
2,521 Views

Hi all, 

 

As we know "logic" data type has 4 states = 0, 1, X & Z, where as "bit" has only 2 states = 0 & 1. 

Generally we can see use of "logic" as data type for all kind of signals on internet :rolleyes:. But I have read in book that for 2 states logic we can use "bit" as datatype.  

So, my question is, 'can we use "bit" data type for those signals like clock or reset which have only 2 states 0 or 1 ?.' :confused: 

If no then why we can not use it, and if yes then what is advantage of using "bit" over "logic".  

 

module test_example 

input bit clk , // system clock 

input bit reset_n // system reset  

); 

 

In this is example I have use bit as datatype for clk and reset_n signal. because it is obvious that clock can not be X or Z. So there are many signals that will not be X or Z then why we used logic datatype for those instead of bit. 

I hope I am clear with my doubt. If anybody has answer for my question, please explain me. All answers are welcomed here..:)
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4 Replies
Altera_Forum
Honored Contributor II
1,144 Views

Most people use logic when they could have used bit. The advantage of using logic is that you will see unknowns in simulation if something hasnt been given a value, or you get multiple drivers somewhere. With bit, errors may not be so obvious as X will not propogate and you'll only get a '0'. 

 

But you are right, bit and reset should always be '1' or '0', so having them as bit wont really hurt.
Altera_Forum
Honored Contributor II
1,144 Views

 

--- Quote Start ---  

 

As we know "logic" data type has 4 states = 0, 1, X & Z 

 

--- Quote End ---  

 

 

std_logic data type has 9 states: "U, X, 1, 0, Z, W, L, H, - " 

u: Uninitialized  

x: Unknown 

1: Logic 1 

0: Logic 0 

Z: High impendance 

W: Weak signal, can't tell if it should be 0 or 1 

L: Weak signal that should probably go to 0 

H: Weak signal that should probably go to 1 

-: Don't care. 

 

 

--- Quote Start ---  

 

In this is example I have use bit as datatype for clk and reset_n signal. because it is obvious that clock can not be X or Z.  

--- Quote End ---  

 

 

In your example, U state can be useful if you forget to initialize a signal in your component testbench.
Altera_Forum
Honored Contributor II
1,144 Views

 

--- Quote Start ---  

std_logic data type has 9 states: "U, X, 1, 0, Z, W, L, H, - " 

u: Uninitialized  

x: Unknown 

1: Logic 1 

0: Logic 0 

Z: High impendance 

W: Weak signal, can't tell if it should be 0 or 1 

L: Weak signal that should probably go to 0 

H: Weak signal that should probably go to 1 

-: Don't care. 

 

 

 

In your example, U state can be useful if you forget to initialize a signal in your component testbench. 

--- Quote End ---  

 

 

The OP is asking about Verilog. Std_logic is a VHDL concept.
Altera_Forum
Honored Contributor II
1,144 Views

thank you, Tricky for your reply.  

And yes JRL this question is about Verilog I am failed to mention that.
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