Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
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MAX V CPLD IO Pin value

Altera_Forum
Honored Contributor II
‎05-10-2012 10:03 AM
1,157 Views

Hi, 

 

We are using MAX V CPLD 5M1270ZT144I5 for our project. 

We would like to know the default value (high, low or high impedance) of the max v cpld (5M1270ZT144I5 ) io pins when powered on without programming the CPLD. 

Is there any possibility to drive the IO pins to high impedance when powered ON without programming the CPLD?
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Altera_Forum
Honored Contributor II
‎05-10-2012 01:55 PM
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As with other Altera chips, the unprogrammed state and state during configuration phase is "Input with weak pull-up". It can't be changed.

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