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MAX V Exposed pad solder reflow problem

Nakaj
Novato
2.830 Vistas

 

A reflow soldering failure occurred on the exposed pad on the bottom of the QFP64
pin device of the MAX V device. Please let me know if there is a recommended
pattern layout for Exposed Pad.
Please let me know if there is a recommended value for the number and diameter of
through holes to connect the exposed pad to the GND pattern.

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1 Solución
Fakhrul
Empleados
1.712 Vistas

Thanks for your response, I now transition this thread to community support. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.


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16 Respuestas
FvM
Colaborador Distinguido II
2.778 Vistas

Hi,
what kind of failure do you observe, missing connection or short to other pins?

I see a previous discussion related to 64-pin EQFP package https://community.intel.com/t5/Programmable-Devices/Max-V-Stencil-Design-64-Pin-Plastic-Enhanced-Quad-Flat-EQFP/m-p/1574520#M94757

I think, a comfortable option is to place vias beneath the exposed pad, this way you don't need to care for solder drain through vias. As mentioned in my previous post, EQFP package has the problem of clearance tolerance between pad and PCB, about 0.05 to 0.15 mm. You need to supply suffient solder paste to safely bridge the gap.

 

Regards
Frank 

Nakaj
Novato
2.757 Vistas

Thank you for your reply.

We have an issue with exposed pad not being connected. There may not be  enough solder.

Is there reccomended pattern layout for PCB?

 

Regards

Nakaj

 

 

Nakaj
Novato
2.739 Vistas

 

Please also tell me the recommended thickness of the solder mask.

 

Regards,

Nakaj

Farabi
Empleados
2.706 Vistas
Nakaj
Novato
2.675 Vistas

Thank you for your reply.

But I would like to know about  reccomended pattern layout for PCB  and recommended thickness of the solder mask of MAX V QFP64 device.

 

Regards

Nakaj

Nakaj
Novato
2.540 Vistas

Thank you for your reply.

If you find a solution please let me know.

 

Regards

Nakaj

Fakhrul
Empleados
2.477 Vistas

Hi Nakaj,


You can check it here: AN 353: SMT Board Assembly Process Recommendations


Hope that helps and do let me know if I can assist you further.


Regards,

Fakhrul


Nakaj
Novato
2.438 Vistas

Thank you for your reply.

 I would like to know about  recommended thickness of the solder mask(stencil?) of MAX V QFP64 device.

About  reccomended pattern layout for PCB, I found a Cadence and mentor graphics CAD data in Intel website.

PCB design engineer tries to analyse it.

Regards

Nakaj

 

 

FvM
Colaborador Distinguido II
2.410 Vistas

Hi,
stencil thickness is usually chosen by the assembly service provider depending on PCA technology and used pad range. As mentioned above, problem with EQFP package is the 0.05 to 0.15 mm range of exposed pad clearance. If the parts have typical 0.1 mm clearance, 120 µm standard stencil thickness should work, but for maximal 0.15 clearance you'll probably want a thicker stencil, e.g. 180 µm if it's still compatible with small pads used on the board.

I'm presuming that you have industry standard reflow profile as suggested in AN353, because another possible reason for solder failure is "cold solder joint".

Regards
Frank

Nakaj
Novato
2.350 Vistas

Thank you for your reply.

your answer is very helpful.

 

Regards

 

Nakaj

Nakaj
Novato
2.151 Vistas

Hi,

Please let me know manufacturer's recommended conditions for MAX V rework(IC mounting by hand soldering).

For example,heating temperature, heating time, tools etc.

Is there a risk of overheating the IC during rework? (Deterioration, impact on lifespan, etc.)

Regards

Nakaj

 

 

Fakhrul
Empleados
1.864 Vistas

Hi Nakaj,


Apologies for the delay due to the end-year and New Year holidays. As mentioned in the AN353, you may refer to the latest IPC-A-610D Standard.


Regards,

Fakhrul


Nakaj
Novato
1.845 Vistas

Thank you so much for your reply.

But my question is still not resolved. 

Please tell me the temperature and heating time of the heater when removing the IC. How can I evaluate the effect on the circuit components on the back side of the IC to be removed?

 

Regards

Nakaj

Fakhrul
Empleados
1.774 Vistas

Hi Nakaj,


You can refer to AN 353: SMT Board Assembly Process Recommendations, and check the rework section where all the requirements are mentioned. I’ve looked through our internal documents, and this is the best information we have available.


Regards,

Fakhrul


Nakaj
Novato
1.745 Vistas

 

Thank you for your reply.

We decided not to do the rework due to customer request.
This concludes my questions.

 

Regards

Nakaj

 

 

Fakhrul
Empleados
1.713 Vistas

Thanks for your response, I now transition this thread to community support. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.


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