Hello all,
I have created a test design running on 10M08 Evaluation Kit. Its task is to alter the PLL output frequency and provide it to output pin. The fin is 50MHz from the onboard clock source. The design uses up/down two buttons that allow me to select the desired frequency. The aim is to select the output frequency in the 1-400MHz range with 1 MHz step. I use ALTPLL_RECONFIG IP core for this task. Created an array of settings for counters (n,m,k,c0) for each frequency in the range with a python script. A state machine controls the process of the pll configuration and the sequence of writing the parameters into the ALTPLL_RECONFIG block. The output pin is configured as 3.3V LVTTL. I'm aware that the 400MHz output frequency is out of range for this pin since Qaurtus Prime gives a warning that it supports max 125MHz. But this is only a test design for check how to recofigure PLL block, and despite this limitation I'm able to see 400MHz waveform on the output pin with an oscilloscope when the ALT_PLL is configured to this frequency. Looks like the design works well in the full required range with the exception of 257MHz output frequency. All output frequencies work as expected but when I select the 257MHz I get 1MHz. The settings for the ALTPLL_RECONFIG are as follows: N=25, K(VCO postscaler)=2, M=257, C0=2.
Do you have any suggestions what might be wrong with these values? The Fout equation gives
Fout=(fin*M)/(N*C0)=50*257/(25*2)=257MHz
and for Fvco is
Fvco=fin*M*K/N=50*257*2/25= 1028MHz
which is in the range 600-1300 specified in the datasheet.
Below I attach a screenshot from SignalTap Analyzer session that shows the sequence used for ALTPLL_RECONFIG configuration
The fout_index signal is just an index in an array of predefined setting values. The value 100h corresponds to 257MHz frequency. The counter_type, counter_param, data_out, write_param, reconfig are input signals for ALTPLL_RECONFIG and reconfig_busy is an output busy signal from ALTPLL_RECONFIG IP core.
Best regards
Link Copied
