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Quartus: How to debug why Synthesis is eliminating logic from the design

YigalB1
Beginner
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The Synthesis eliminated large parts of my design.

There was a warning about few logic signals that they are not driving any logic, although to me it looks like the RTL is OK.

I tried a workaround that works - to take bussed and signals that are output from one block and input to another block, and make them output of the top level.

I assume there is an attribute for the Synthesis that is targeted to solve this issue - I will search and learn that.

Yet my question is: Does it mean there is a deeper bug in my design? Because if the synthesis is eliminating logic, it means this logic is either not influencing the outputs, or have wrong setting (such as output is always zero). 

Any idea how to solve this?

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FvM
Honored Contributor II
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Hi,
basically unexpected removal of logic suggests a design error, may be wrong logic condition, missing clock or part of the design unintenionally held in reset.

Problem is, if a complete logic chain is removed in synthesis, it's not easy to see where it's broken. Creating auxiliary output or keeping debug signals with respective synthesis attributes (e.g. noprune for registers) and watch them in Signaltap is a possible option. Diagnosis is probably simpler in RTL simulation.

Regards

Frank

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sstrell
Honored Contributor III
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No, like it says, if you don't connect a signal to anything, it can get optimized away.  Use Virtual Pin assignments in the Assignment editor to connect signals to stubs of logic to avoid this.

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FvM
Honored Contributor II
262 Views

Hi,
basically unexpected removal of logic suggests a design error, may be wrong logic condition, missing clock or part of the design unintenionally held in reset.

Problem is, if a complete logic chain is removed in synthesis, it's not easy to see where it's broken. Creating auxiliary output or keeping debug signals with respective synthesis attributes (e.g. noprune for registers) and watch them in Signaltap is a possible option. Diagnosis is probably simpler in RTL simulation.

Regards

Frank

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