MAX10 Development kit Strange clock issues.

[Altera_Forum]

Hey, I'm working on a prototype design using the MAX 10 Development Kit, and recently something strange happened. 

 Now, in order to get the required amount of output pins required to interface with other devices in my design, I'm using a Terasic HSMC to GPIO Daughter Board. So to access the GPIO pins I'm reliant on using the HSMC_TX_D_P[x] output bus, as well as the HSMC_CLK_OUT_p[1-2] for clock outputs. Having only a single device connected to the FPGA everything worked just fine, I was able to output a 20MHz clock on the HSMC_CLK_OUT_p[1] pin, and the other outputs worked just fine.  However, when I tried loading up the design yesterday, something had changed. The output pins were no longer useable, and the clock signal at the pin had gone from 20MHz, to some unstable 200Hz'ish signal.  I realized that the output issue was due to me using elements 0-4 AND element 7 of HSMC_TX_D_p, without actually assigning elements 5-6, leading to quartus renaming the pins to some strange legacy default. This issue solved itself when I added outputs to the unused elements.  However, the clock issue still remains. These are the warnings related to the clock signal.  Warning (176674): Following 2 pins are differential I/O pins but do not have their complement pins. Hence, the Fitter automatically created the complement pins. Warning (176118): Pin "HSMC_CLK_OUT_p" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "HSMC_CLK_OUT_p(n)" Warning (15064): PLL "SourceCLK:SRCCLKPLL|altpll:altpll_component|SourceCLK_altpll:auto_generated|pll1" output port clk feeds output pin "HSMC_CLK_OUT_p~output" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance  I'm thinking that there might be an issue related to the complement pin HSMC_CLK_OUT_n[1], and if I wanted to add one, how would I do so?  EDIT, Using the GPIO Lite IP block to add a complement pin does not seem to solve the issue. However it removed the differential warnings. The issue still remains, presumable because the output is fed via non dedicated routing (see warning 15064).