Can anyone tell what happens to the MAX10 after JTAG operation? Its I/Os float, its flip flops being cleared, it gets DEV_CLR, etc
We have two MAX10 devices on our board connected together on a chain. one of the FPGAs controls the board reset.
We see that after every operation, even after "Verify" of one of the FPGAs (it doesn't matter which), our board gets reset.
All configuration pins and JTAG pins in Intel MAX 10 devices are dual-purpose pins. The configuration pins function as configuration pins prior to user mode. When the device is in user mode, they function as user I/O pins or remain as configuration pins.
You can refer to Intel® MAX® 10 FPGA Configuration
User Guide for more details: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/max-10/ug_m10_config.pdf
The I/O state of the pin depends on what is set by the user on Quartus. Unused pin will be in week pull (set using unused pin settings) which means HIGH state or 1. You might get this problem from the transition from configuration mode to user mode. The I/O is expected to be in HIGH mode during the configuration and the state after that will depends on what is set by the user. You might also want to check if you have reset it as reset in user mode.