We have a board designed with a MAX10 (10M16) with dual supply.
Due to a regulator error, the stable 2,5V that was to be fed to VCCA# pins is a "not so stable" (still to be estimated) 3,3V.
From what I read in datasheets, 3,3V is still under the absolute max rating, but pretty high. Is it correct to expect damages on the CPLD in the long term?
However, our main problem is that we use one ALTPLL to generate the CPLD's user clock. With an instable (and too high) VCCA, what consequences can we expect on the reliability of this PLL?
If that helps, the PLL generates 100MHz and 250MHz from 50MHz.
I understand your concern and I will try my best to answer your inquiry.
You can refer to Intel® MAX® 10 General Purpose I/O User Guide on table 14 to look at Voltage Tolerance Maximum Ratings for 3.3 V. Thus, it should be okay if the value is in the range specified in our document.
Thank you for your answer.
However, the table refers to VCCIO pin(s). These pins are correctly fed with 3,3V in our design.
The concern is only about the VCCA# pins.
Or did I misinterpret something?
My understanding is that VCCIO pins are the ones powering the CPLD's IO banks, while the VCCA pins are dedicated to PLL analog block.
I got this from https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/dp/max-10/pcg-01018.pdf page 16 and https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/max-10/m10_datasheet.pdf page 7.
The latter also mentions the absolute maximum ratings I mentioned in my first message on pages 4&5.
Sorry for the confusion. Yes you are correct. As stated in the document, conditions outside the range listed in the absolute maximum ratings tables may cause permanent damage to the device. Device operation at the absolute maximum ratings for extended periods of time may have adverse effects on the device.
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