I'm considering using the HS LVDS interface on MAX10 device, not constantly but with time division, al follows:
Applying the LVDS Clock for T1 time, and transferring Data after the link is established (after PLL is locked, data alignment, etc.), Then following with "sleep time" (no Clock or Data) for T2 time, and all over again.
The rising questions are:
1. Will the MAX10 function properly (The intended operation is to apply a constant Clock, and not as I described).
2. What is the minimum / maximum PLL lock time in the MAX10 device?
1. It sounds like it will be working fine.
2. You can find PLL specification from page 26 of this link: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/max-10/m10_datasheet.pdf
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