MAX10M04 / Quartus Prime Lite Edition

[Gigiz]

Good morning,
I'm completing a project with MAX10M04 FPGA and Quartus Prime 20.1 Lite Edition software.
The project is in the final phase, everything works fine but I have a very strange problem: I used the schematic for the whole FPGA project and using the same component I built "1Encoder" four times it gives me problems just by connecting the hardware of the 4th component.
Not connecting this all the whole project works perfectly.
Are there any limitations using the "Lite Edition"?
I attach the FPGA project and the wiring diagram of my board.
Thanks.

[Nurina]

Hi,

I tried compiling your project on my machine and it seems to work fine. Can you let me know what OS are you using and can you attach a picture of the error message you receive?

Thanks,

Nurina

P/S: Feel free to give Kudos to comments you find to be helpful.

[Gigiz]

Hello Nurina,

I'm using Windows 10 OS.

I have not error messages in compiling process, I have only some warning messages.

The problem is on board functionality:

I have 4 quadrature encoder counter, in the schematic named "4Encoder", inside it I have 4 instance of single counter named "1Encoder" with lpm_counter5 functionality.

The problem is very strange: 1st, 2nd, 3th encoder running and counts properly, the 4th counter works with anomaly mode and influence the others (seems that reset the other counters).

Thanks,

Gigi

[Nurina]

Hi Gigi,

So just to clarify, the anomaly mode is that when you add the 4th counter it doesn't function correctly while causing the other counters to function wrongly? Is there anything more to it?

Regards,

Nurina

[Gigiz]

Hi Nurina,

The FPGA project is with all 4 counters, I have the problem with the first 3 counters only when I connect the 4th counter hardware signals:

EXT_ENC4_A on pin 85

EXT_ENC4_B on pin 86

EXT_ENC4_Z on pin 87

EXT_ENC4_ALARM on pin 88

Regards,

Gigi

[Nurina]

Hi Gigi,

Have you simulated your design and confirmed the functionality? You should verify that your logic on RTL viewer are connecting as intended.

Regards,

Nurina

[Gigiz]

Hi Nurina,

How I can do it ?

Where can I find RTL viewer ?

I have not experience with it, can you help me please ?

During the compile process I have some warning, are there somethings to need fix ?

Thanks,

Gigi

[Nurina]

Hi Gigi,

You can refer to page 3 of this document on how to use it: https://www.intel.cn/content/dam/altera-www/global/zh_CN/pdfs/literature/hb/qts/qts_qii51013.pdf

The Intel FPGA YouTube channel has some videos on it as well, you can start here: https://www.youtube.com/watch?v=nWIGG0eWpJU

Part 2 of the video lecture is available here: https://www.youtube.com/watch?v=gFclHedSomA

In most cases warning messages can be ignored. Can you attach a photo of the warning messages here so I can verify that it can be ignored?

Thanks,

Nurina

[Gigiz]

Hi Nurina,

In attachment you have the warnings report, you can also compile my project and look it.

I try to look the documentation and simulate my project ...

Can you simulated my project ?

Best Regards,

Gigi

[Gigiz]

Hi Nurina,

I have not solve my problem yet, did you see the warnings report ?

Best Regards,

Gigi

[Gigiz]

Hi Nurina,

my project running at 99.99%, I made a very simple modification...

I attach the project, look at top level schematic "EtherCAT", you can see the signals "enc4_A" and "enc4_B" connected directly to ground.

In this condition all counter works properly and all the project runs, I have only 2 signals not connect (but I use theese only for monitor).

What can be the reason ?

Thanks.

Best Regards,

Gigi

[Nurina]

Hi Gigi,

Yes, I did. You can ignore most of them, but I suggest you do something about the multiple warnings about overlapping block or symbols. Follow the solution available here: https://www.intel.com/content/www/us/en/programmable/quartushelp/13.0/mergedProjects/msgs/msgs/egdfx_symbols_overlap_error.htm

Also, I've checked your pin planner and it seems that you are using a clock pin for the EXT_ENC4_ALARM node, I think that's the cause of the problem. Use a differential pin for this node like you did with the other ALARM nodes.

Regards,

Nurina

[Gigiz]

Hi Nurina,

the hardware circuit is just connected to EXT_ENC4_ALARM and it is configured as standard input (I think).

I use other signals connected to others clock pin without problem.

The external clock is on pin 27.

I have also many warnings #332060, How I can configure the CLOCK input and associated it to the other signals ?

Gigi

[Gigiz]

Hi Nurina,

I have fixed all overlap blocks warnings ID 275059.

I have many warnings ID 332060 and one ID 332068 (no clocks defined in design),

how can I fix them ?

Thanks.

Best Regards,

Gigi

[Nurina]

Hi Gigi,

I don't see signals "ENC4_A" and "ENC4_B" connected to the ground in your new design file. Can you explain what those signals, along with the alarm signal do?

Can you use the SignalTap logic analyzer on the 4Encoder to probe and debug the behaviour of internal signals during normal device operation? SignalTap can be used to monitor your real time signal, so you can find the root cause of the problem.

Here's a document that can help you understand SignalTap: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/qts/qts_qii53009.pdf?wapkw=signal%20tap%20

There are also some training courses about SignalTap available on Intel FPGA's YouTube channel: https://www.youtube.com/watch?v=RtPqQ25hSIk

Regards,

Nurina

[Gigiz]

Hi Nurina,

thanks for the informations, ENC4_A and ENC_B are in the input of "EtherCAT" block at topo level design.

The "ENC4_ALARM" is not a problem.

Best Regards,

Gigi

[Gigiz]

Hi Nurina,

How can I fix the 332060 and 332068 warnings ?

Thanks.

Best Regards,

Gigi

[Nurina]

Hi Gigi,

You can fix those warnings by constraining the clock signals using Timing Analyzer. Go to Tools->Timing Analyzer.

Here is a reference on it: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/manual/mnl_timequest_cookbook.pdf

Regards,

Nurina

[Nurina]

Hi Gigi,

We did not receive any response to the previous answer that I have provided, thus I will put this case to close pending. Please post a response in the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you with your follow-up questions.

Regards,
Nurina

PS: If you find any comment from the community or Intel Support to be helpful, feel free to give Kudos.

[Gigiz]

Hi Nurina,

Sorry, what is your previous answer ?

I have not made deep test as you suggestion me, I need time ...

The problem is very strange, I solve it if I disconnect two signals and connect the input block directly to groud (as attached picture).

Best Regards,

Gigi

[Nurina]

Hi Gigi,

My previous reply suggests you to solve the timing warnings by constraining the clock signals using Timing Analyzer.

So you're trying to figure out why that happens? By solved do you mean that all 4 counters work together as expected?

Regards,

Nurina