MAX10 RSU unconstrained clocks

[Altera_Forum]

Hello, I'm getting two errors from the reconfiguration module in the MAX10 FPGA. 

I'm trying to use the dual_boot_cfg module and onchip_flash modules and am getting TimeQuest errors reporting unconstrained clocks in the modules. Is this something I can safely ignore or are there sdc constraints that I can apply to remove them? The errors are generated from inside the encrypted modules so I can't determine what constraints to apply. Any help if greatly appreciated. I'm using Quartus Prime Lite Edition V 17.0.1 Build 598.  Build warnings: Warning (332060): Node: Main:main|MAX10_RSU_Sys:max10RSUSys|altera_dual_boot:dual_boot_cfg|alt_dual_boot_avmm:alt_dual_boot_avmm_comp|alt_dual_boot:alt_dual_boot|ru_clk was determined to be a clock but was found without an associated clock assignment.  Main:main|MAX10_RSU_Sys:max10RSUSys|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|flash_se_neg_reg

[Altera_Forum]

Try setting the 'clock frequency' of both the modules , than compiling with the default values.

[Altera_Forum]

Here is the QSys config for the flash and dual boot module. The clock setting is already set properly to 80MHz and this is still error is still generated. 

It seems like there is a missing constraint in the generated modules. Am I missing something?  https://www.alteraforum.com/forum/attachment.php?attachmentid=13864  https://www.alteraforum.com/forum/attachment.php?attachmentid=13865

[Altera_Forum]

Do you have SDC constraints for the base clock(s) coming into the FPGA and any other generated clocks coming from, say, PLLs outside the system? Even though you shouldn't have to constrain clocks internal to a Qsys system, you still have to constrain what's outside the system.

[Altera_Forum]

I have a 50MHz clock coming into the FPGA: CLOCK_50 

This signal routes to the internal pll input. The internal Pll generates 2 clocks, 50MHz and 80MHz. The flash and dual config modules run off the 80MHz clock.  I have the following constraints in my sdc file: create_clock -name {CLOCK_50} -period 20.000 -waveform { 0.000 10.000 } [get_ports {CLOCK_50}]  set_clock_uncertainty -rise_from [get_clocks {CLOCK_50}] -rise_to [get_clocks {CLOCK_50}] 0.020  set_clock_uncertainty -rise_from [get_clocks {CLOCK_50}] -fall_to [get_clocks {CLOCK_50}] 0.020  set_clock_uncertainty -fall_from [get_clocks {CLOCK_50}] -rise_to [get_clocks {CLOCK_50}] 0.020  set_clock_uncertainty -fall_from [get_clocks {CLOCK_50}] -fall_to [get_clocks {CLOCK_50}] 0.020   derive_pll_clocks derive_clock_uncertainty  Here is a screen shot of my Clock Status Summary from Quartus: https://alteraforum.com/forum/attachment.php?attachmentid=13866&stc=1

[LYona]

I have the same problem. is there solution?