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Valued Contributor III
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MAX10 - SignalTap makes project not working

Hi 

I have a custom board with MAX10 10M25SAE144I7G. When I try to add a lot of nodes (std_logic, and std_logic_vectors) and memory is almost full after compilation the project stops working. SignalTap does not recognise some of the state machines (no names, i can see only 00), some of my VHDL components stop working etc. When I remove some nodes (for example 70% usage of the memory) and recompile the project works properly.  

What could be the reason of such behaviour? What can i do? Do You some advices?
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Valued Contributor III
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Re: MAX10 - SignalTap makes project not working

Do you set timing constraints on the clk? 

Check the maximum freq of the clock of the design.
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