HiI have a custom board with MAX10 10M25SAE144I7G. When I try to add a lot of nodes (std_logic, and std_logic_vectors) and memory is almost full after compilation the project stops working. SignalTap does not recognise some of the state machines (no names, i can see only 00), some of my VHDL components stop working etc. When I remove some nodes (for example 70% usage of the memory) and recompile the project works properly. What could be the reason of such behaviour? What can i do? Do You some advices?