MAX10 can't accept 125 MHz clock without timing violations

[Altera_Forum]

Hi. 

I'm using quartus 15.0.0 64-bit on Windows 7 pro. I'm working on a design that uses an MAX10 (10M08SAU169C8). The design calls for two clock domains. The first is 50 MHz and the second is 125 MHz. The 50 MHz clock domain is used for the majority of the design (well less than 50% utilization in all categories). The 125 MHz clock feeds an instantiated PLL which is to provide a 10 MHz output on C0. The 10 MHz output from the PLL clocks the ADC block for the temperature sense function. When I compile the design I get timing errors in all three temperature/speed models suggesting that the restricted fmax is below 100 MHz due to a low minimum pulse width violation. I do understand that the tool is saying I can't run over 98.something MHz. I don't know what a low minimum pulse width violation is or what exactly the restricted FMAX means.  I thought that perhaps my other logic was the problem so I created a test design that includes only the PLL, the ADC, and a single registered output bit from the ADC. Again, the 125 MHz goes only to the PLL which provides an 10 MHz output for the rest of the design. When I compile the new project with or without the proper pin assignments (for my board) I still get restricted fmax low minimum pulse timing errors and a restricted fmax under 100 MHz.  I've been poking around the datasheet and can't find anything to suggest that this device can't utilize an 125 MHz clock. I'm sure I'm doing something wrong as I'm clearly no timing expert.  Any suggestions on how to appease the timing tools? I've attached an archive of my test project for reference.  Thanks in advance.

[Altera_Forum]

The error message in this case is a bit of a red herring. The issue is you haven't defined the clock output of the PLL. You can do this by adding this command to your SDC file: 

 derive_pll_clocks  That will trace the input clock and create the necessary generated clock commands.  Tim MN FAE

[Altera_Forum]

This looks like it is something to due with the ADC timing requirement. I modified you design and removed the ADC and it works fine. The design looks like the clock is only going to the PLL, so I don't understand why the ADC timing is involved, but I would send your design to the mysupport area of Altera, and see if they can tell you if it's a tool issue. 

 I have a design that is running > 162 MHz in Max 10 but I'm not using the ADC and I'm using the dual supply part.  Pete

[Altera_Forum]

I believe the ADC is the issue, but he was dropping the clock from 125MHz to 10MHz with the PLL, but since he didn't have the generated clock statements or a derive_pll_clocks statement to generate them automatically, it was assumed to be 125MHz (same as the input). Once you put in the correct clocks, the minimum pulse width errors go away.