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David_Ben_Hamou
Beginner
154 Views

MAX10 i/o state during Device Initialization (before user mode and after configuration time)

Good afternoon,

I have my output pins during the device initialization phase which has a level of 1.2V (3.3V I/O power Bank) and I have 10K pull down on my output signal (LVCMOS 3.3V). I don't know why I have this voltage level (I was expecting 0V).

I need to know what is the I/O state during Device Initialization (before user mode and after configuration time) ?

It is possible to change the I/O state during device initialization ?

 

 

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3 Replies
AminT_Intel
Employee
140 Views

Hello David, 

 

Hope you are doing well. 

 

I need to know what is the I/O state during Device Initialization (before user mode and after configuration time) ?

There are four stages in device operation: Power Up, Configuration, Initialization and User Mode. 

During initialization mode,  internal logic and I/O registers are initialized and I/O buffers are enabled. When initialization is finished, the INIT_DONE pin is released and pulled high by an external pull-up resistor. 

 

It is possible to change the I/O state during device initialization ?

No. The I/O state can only be changed in User Mode.

 

I hope this answer helps. 

David_Ben_Hamou
Beginner
136 Views

Hello,

Thanks for the reply.

I need more information about the following point:

During initialization mode, internal logic and I/O registers are initialized and I/O buffers are enabled.

 

What is the behavior of I/O pins of the FPGA during this phase ('Z' or wealky pull-up or something different) ?

Thanks

AminT_Intel
Employee
127 Views

Hello Ben,

 

You can refer on this document: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/cfg/cfg_cf51001.pdf (Page 1 Figure 1). The figure gives information in details about I/O state of each phases. 

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