MAX10 pin too close to PLL clock

[Altera_Forum]

Hi all, 

I install a new Quartus 16.0 and faced with the problem that the project compilation with error message. Error (18496): The Output CH4_TXCO in pin location 29 (pad_9870) is too close to PLL clock input pin (CLK_48MHz) in pin location 28 (pad_2) The project uses family "MAX 10", device 10M08SAE144C8GES. The Quartus 15 .1 project compiles fully, without errors. How to solve a problem ? Use only Quartus 15.1 ? Thanks. http://www.alteraforum.com/forum/attachment.php?attachmentid=12213&stc=1

[Altera_Forum]

I have the same problem. Is there any solution?

[Altera_Forum]

You need to change CH4_TXCO pin location away from PLL clock input. SI affects to this pin because of close location to PLL clk input. So Fitter occurs error.

[Altera_Forum]

This error not occurs in Quartus 15.0 SW. So it have to have another solution.

[Altera_Forum]

Maybe device characterization seems be changed, adding restrictions. I don't know the reason.

[Altera_Forum]

I have the same question, is there any other way to solve it?

[Altera_Forum]

Quartus 16.0 version will appear if using ALTPLL …………

[Altera_Forum]

Here is the error cause, could you read this link? 

http://sw-web.altera.com/tools/quartuskit/16.0/current.linux64/linux64/quartus/common/help/webhelp/index.htm#msgs/msgs/efiomgr_output_too_close_to_pll_clock_input.htm Use another pll ref_clk input, or create clock from other pll, or change the error target pin location. I don't think all IO standard user IOs are prohibited adjacent to PLL clk in, I gues some IOs are restricted due to affection of switching noise.

[Altera_Forum]

Hi, 

 the is case is actually documented in the MAX 10 FPGA Signal Integrity Design Guidelines (https://www.altera.com/en_us/pdfs/literature/hb/max-10/m10_sidg.pdf#page=7). The only way I can think of to get a solution for this issue in 16.0 is to file a service request.  Cheers, fade

[Altera_Forum]

Hello, 

i have the same problem that you had. At the end how did you solve it? thank you for your answer  Riccardo

[Altera_Forum]

--- Quote Start ---  Hello, i have the same problem that you had. At the end how did you solve it? thank you for your answer  Riccardo  --- Quote End ---   Hi. To solve "Error (18496)" need use Quartus 15.1 or re-design of PCB. :(