Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
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MAX10 remote system upgrade

Honored Contributor II



I am currently implementing the remote system upgrade for the MAX10/04 but have a few issues. I've been googling but haven't found any related information. Hopefully those of you have experience with this MAX10 configuration can throw some lights for me:-P 


1. there are a few options of the configuration mode including dual/single image, or compressed/uncompressed image, we configured these when generating the altera_onchip_flash core. However after building the quartus project, is there any way that we can read these configuration from the flash , ie, the header of the RPD file?  


2. when use the compressed image mode, as stated in the MAX10 datasheet, a minimum of 30% compression ration is required. My compression ration is around 50~60% with 65% resource usage, which is not a matter as now. However I'm a bit concern about this compression ratio as when the design grows the device can be rather full (ie 99% full), if that happens will the compression ratio achieve 70%?  


3. the timing issue. the only guaranteed present clock resource is the on chip oscillator whose frequency ranges from 55 to 116 MHz, this clock will also be the clock input to the altera_onchip_flash. In the IP configuration dialogue, I used 116MHz as the frequency input so this is hitting the timing limit. However I found the timing constraint constantly failed if I put a little bit more logics around the flash, even a change of version number from 1 to 2!!! I didn't see other people have similar issue, so wondering whether I did it correctly, any thought? The failed path is in the data path from one register to another which is quite far away from each other in the placement view. Can we place any restriction to get around with it? 


Thanks in advance, 


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