MAX10 simulation of ALTPLL created in Platform Designer does not work.

[Ken18]

Dear Sirs,

RTL simulation of ALTPLL created in Platform Designer does not work for Quartus Prime Lite 23.1.1 with MAX10.

If I use ALTPLL as a standalone IP it works fine.
Someone please give me advice.

[Yarko]

Hi,

If you use Questa, you need to connect the library, you can do it in your run.do script or setup it through the GUI:

-L altera_mf_ver -L altera_mf

I hope this solves the problem.

[Ken18]

Thanks a lot,

I use Questa Intel FPGA.

If possible, please tell me a more specific method.

[AqidAyman_Intel]

We sincerely apologize for the inconvenience caused by the delay in addressing your Forum queries. Due to an unexpected back-end issue in our system, your Forum cases, along with others, did not get through as intended. As a result, we have a backlog of cases that we are currently working through one by one.

Please be assured that we are doing everything we can to resolve this issue as quickly as possible. However, this process will take some time, and we kindly ask for your patience and understanding during this period. The cases will be attended by AE shortly.

We appreciate your patience and understanding, and we are committed to providing you with the best support possible.

Thank you for your understanding.

[AqidAyman_Intel]

Hello,

Do you get to solve your issue with the suggested solution by the other community user?

Or do you still need help/support on this question?

Regards,

Aqid

[Ken18]

Dear Sir,

I haven't been able to resolve the issue yet and need your help.

[AqidAyman_Intel]

Hi,

Can you share with us the snapshot of the error message you got when trying to perform the RTL simulation of ALTPLL created in Platform Designer?

Regards,

Aqid

[AqidAyman_Intel]

Hello,

Any updates for the recent request?

[Ken18]

Dear Sir,

An error does not occur, but the C0 and C1 waveforms do not appear.

Please refer to the snapshot below.

Screen of Platform Designer
-> PD_altpll.jpg

Screen of RTL Simulation
-> RTL_Sim.jpg

Best Regards.

[AqidAyman_Intel]

Hi Sir,

Thank you for the information. May I know if you are willing to share the design file for me to duplicate the issue?

Thanks.

[Ken18]

Dear Sir,

I will send you the design file.

Best Regards.

[FvM]

Hi,

looks like areset input is defined in PLL but unconnected in platform designer.

[Ken18]

Dear Sir,

Thanks for your advice.

I tried to connect the areset input externally, but the result was the same.

Best Regards. 

[AqidAyman_Intel]

Hello,

May I know if you have any further questions about this issue?

[AqidAyman_Intel]

Hi Sir,

Can I connect with you by email on this issue?

Regards,

Aqid

[Ken18]

Dear Sir,

Sorry for the late reply.

Welcome to  contact  me by email.

Best Regards. 

[AqidAyman_Intel]

As we do not receive any response from you on the previous question/reply/answer that we have provided. Please login to ‘https://supporttickets.intel.com/s/?language=en_US’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.