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MAX10 soft lvds rx

BJona
Novice
210 Views

Hello,

I'm trying to understand the behavior of the soft lvds IP from the documentation.

1 - When digging into the generated .v files, there are some DDIO registers instantiated although there are no option asking which clocking scheme is used. (DDR or not)

Does this mean that the clock is considered as a DDR one?

2 - When setting the data rate in Mbps and the deserialization factor is above 4, an input clock is proposed. It can be the exact same rate than the data rate or half or a third and so on. Why? I could understand the half clock rate if using a DDR clock, but I don't get why the third, the fourth etc... of the base data rate are suggested. 

Thank you by advance for you help.

 

John

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1 Solution
EngWei_O_Intel
Employee
183 Views

Hi John

The Intel MAX 10 devices use registers and logic in the core fabric to implement LVDS input and output interfaces:
• For LVDS transmitters and receivers, Intel MAX 10 devices use the the double data rate I/O (DDIO) registers that reside in the I/O elements (IOE).
• For the LVDS serializer/deserializer (SERDES), Intel MAX 10 devices use logic elements (LE) registers.

If you are using internal PLL mode, internally, it will be used to generate clocks needed by the LVDS IP. There is a rule to select the data rate and the inclock which is "INPUT_DATA_RATE (in Mbps) * INCLOCK_PERIOD (in microseconds) must be an integer (1 to 30)". You will be seeing error if this condition isn't met.

If you are using external PLL, you need to provide 3 clock sources which are rx_inclock, rx_syncclock and rx_readclock. Table 9 and Section "4.3.1.2.2 Determining External PLL Clock Parameters for Altera Soft LVDS Receiver" in the doc https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/max-10/ug_m10_lvds.pdf further explaining it. 

 

Thanks.

Eng Wei

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2 Replies
EngWei_O_Intel
Employee
184 Views

Hi John

The Intel MAX 10 devices use registers and logic in the core fabric to implement LVDS input and output interfaces:
• For LVDS transmitters and receivers, Intel MAX 10 devices use the the double data rate I/O (DDIO) registers that reside in the I/O elements (IOE).
• For the LVDS serializer/deserializer (SERDES), Intel MAX 10 devices use logic elements (LE) registers.

If you are using internal PLL mode, internally, it will be used to generate clocks needed by the LVDS IP. There is a rule to select the data rate and the inclock which is "INPUT_DATA_RATE (in Mbps) * INCLOCK_PERIOD (in microseconds) must be an integer (1 to 30)". You will be seeing error if this condition isn't met.

If you are using external PLL, you need to provide 3 clock sources which are rx_inclock, rx_syncclock and rx_readclock. Table 9 and Section "4.3.1.2.2 Determining External PLL Clock Parameters for Altera Soft LVDS Receiver" in the doc https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/max-10/ug_m10_lvds.pdf further explaining it. 

 

Thanks.

Eng Wei

View solution in original post

EngWei_O_Intel
Employee
164 Views

Hi John

I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.


Eng Wei

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