MAX10DD devices seem to not support ADC Blocks ?!?

[cjamcki]

we have a design targeting 10M50DDF256I7G.  The device overview claims to support analog features as well as RSU, and some special flash access (not sure what that is but whatever).  However, in Qsys when you try to instantiate an ADC block (single or DUAL) IP core, it complains that the device doesn't support ADC.

Error: modular_adc_0: The selected device part number 10M50DDF256I7G does not support ADC

The pin planner for this device shows the pins having ADC as a pin option (maybe it's just a visual thing, but still).

If i target a 10M50AD device ("AD" vs. "DD"), it allows the ADC IP to be generated no problem.

So, why can't I use it in the DD device, or is not supported (even though the overview says so).

Thanks

[AqidAyman_Intel]

Hi,

I am grateful that the patch file provided helps you to proceed for now. From the current information I have, the target version to implement this fix is on Quartus 24.1 Standard version.

With that, may I know do you need any more support on this?

Regards,

Aqid

[AqidAyman_Intel]

I hope the previous response was sufficient to help you proceed. As we do not receive any response from you on the previous question/reply/answer that we have provided. Please login to ‘https://supporttickets.intel.com/s/?language=en_US’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.