MAX10DD devices seem to not support ADC Blocks ?!?

[cjamcki]

we have a design targeting 10M50DDF256I7G.  The device overview claims to support analog features as well as RSU, and some special flash access (not sure what that is but whatever).  However, in Qsys when you try to instantiate an ADC block (single or DUAL) IP core, it complains that the device doesn't support ADC.

Error: modular_adc_0: The selected device part number 10M50DDF256I7G does not support ADC

The pin planner for this device shows the pins having ADC as a pin option (maybe it's just a visual thing, but still).

If i target a 10M50AD device ("AD" vs. "DD"), it allows the ADC IP to be generated no problem.

So, why can't I use it in the DD device, or is not supported (even though the overview says so).

Thanks

[cjamcki]

sorry, the line should read:

If i target a 10M50DA device ("DA" vs. "DD"), it allows the ADC IP to be generated no problem.

sorry about  that.

[AqidAyman_Intel]

Hello,

I am really sorry for the experience you had. May I know if you okay to share your design to me either by private or if it is simple design and you don't mind you can share it here.

I need the .qar file to replicate the issue from my side for further escalation if needed.

Regards,

Aqid

[cjamcki]

here is a basic project archive.   it has nothing in it except an "adc_bad" qsys file.  when you open it in platform designer, you'll see that it says the DD device is not supported, and you can't generate HDL due to that error.

if you re-target to a device with suffix DA, it doesn't complain.

thanks

[AqidAyman_Intel]

Hello,

Thank you for the design file. What Quartus version that you are using?

[cjamcki]

Quartus Prime Version 22.1 std.0 build 915 10/25/2022 SC Lite Edition

Patches Installed: None

this is a windows version.  we've had similar issues on 20.1 on Linux

[AqidAyman_Intel]

Okay, thank you for the information and the design file. I will escalate this issue to the internal team. I will update you back once I got any feedback on this.

[Pooh_Bear]

Any update on this issue?

I am using the 10M40DD part and have the same problem. Fails to compile with Quartus version 23.1.std

Error (12252): Adc.modular_dual_adc_0: The selected device part number 10M40DDF256I7G does not support ADC

[cjamcki]

this really shouldn't be a difficult question to answer.  i see only two options:

1. the "DD" variant does not not support ADC (documentation error)

2. it does support it but there's a bug in Quartus/Platform Designer.

we were hoping to take advantage of the flash options of the "DD" version, but we intend to use the ADC as well.

we are getting close to ordering components for our program for prototype PCBs, so we really need to know the answer.  If it is, the first above, we will just switch to the "DA" flavor and forgo the flash benefits. 

if it is the second choice above, we would need to know when a patch or variable setting or whatever would be available.  if it is too far in the future, we'd likely switch to the DA part as well.

[AqidAyman_Intel]

Hi,

There is still investigation going on for this issue in Quartus.

Max 10 with "DD" variant should be the same as "DA" variant but with the additional "flash access control" feature. So, it should have the ADC feature.

This is likely to be the number 2 options.

I will definitely update back to you once I got the timeline to avoid this error.

Regards,

Aqid

[AqidAyman_Intel]

Hi,

May I confirm with you, for the Max 10 DA device, the design can be compiled successfully with the IP? If yes, can you please share with me the design or else, the IP parameters setting such as the sequencer, etc?

Regards,

Aqid

[FvM]

Hi,
you can make a very simple test, instantiate the add IP as top level entity. As expectable, failing of adc IP synthesis results in design generation failure.

Error (12252): Adc_bad.modular_adc_0: The selected device part number 10M50DDF256C8G does not support ADC
=>

Error (12153): Can't elaborate top-level user hierarchy

(checked with Quartus Prime Std. 22.1) 

[cjamcki]

you can just take what i sent previously, and change the target device to the DA variant rather than DD.  after doing so, and opening Platform Designer, you don't see the error in the window:

you can generate  HDL successfully (ignore the warning since this is a dummy design and not fully hooked up to anything useful):

as for the parameters of the ADC core, it seems to be rather inconsequential.  I've tried it with single channels, all channels, etc.  and it didn't matter.  the dummy design i previously sent has two of them enabled, as well as the sequencer.  you can open the block to check it out for yourself.

i'm uploading the SAME DESIGN, with only the target device changed to DA vs. DD.  You should be able to show someone else at your company what is going on, and maybe they can help you resolve this.